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Verilog memories are potentially wires

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This commit is contained in:
Jan Decaluwe 2010-07-27 21:12:35 +02:00
parent 7c655e881c
commit 49ed1d7432
1 changed files with 6 additions and 3 deletions
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9
myhdl/conversion/_analyze.py
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@ -407,6 +407,8 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
tree.vardict = {}
tree.inputs = set()
tree.outputs = set()
# hack for assigned mems
tree.outmems = set()
tree.argnames = []
tree.kind = None
tree.hasYield = 0
@ -1269,6 +1271,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
m._read = True
elif self.access == _access.OUTPUT:
m._driven = 'reg'
self.tree.outmems.add(n)
elif self.access == _access.UNKNOWN:
pass
else:
@ -1741,11 +1744,11 @@ class _AnalyzeAlwaysCombVisitor(_AnalyzeBlockVisitor):
for n in self.tree.outputs:
s = self.tree.sigdict[n]
s._driven = "wire"
for n in self.tree.outmems:
m = _getMemInfo(self.tree.symdict[n])
m._driven = "wire"
class _AnalyzeAlwaysDecoVisitor(_AnalyzeBlockVisitor):
def __init__(self, tree, senslist):