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gen func calls excluded

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This commit is contained in:
jand 2004-01-21 11:21:23 +00:00
parent 714092b5bb
commit 4a763cd214
3 changed files with 5 additions and 36 deletions
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7
myhdl/_toVerilog/_analyze.py
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@ -400,7 +400,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
if n in ast.inputs:
self.visit(arg, _access.INPUT)
if ast.isGen:
node.obj = _Generator()
self.raiseError(node, _error.NotSupported, "Generator function call")
elif type(f) is MethodType:
self.raiseError(node,_error.NotSupported, "method call: '%s'" % f.__name__)
else:
@ -549,9 +549,10 @@ class _AnalyzeVisitor(_ToVerilogMixin):
self.refStack.push()
self.visit(node.body, *args)
self.refStack.pop()
y = node.body.nodes[0]
if isinstance(node.test, astNode.Const) and \
node.test.value == True and \
isinstance(node.body.nodes[0], astNode.Yield):
isinstance(y, astNode.Yield):
node.kind = _kind.ALWAYS
self.require(node, node.else_ is None, "while-else not supported")
self.labelStack.pop()
@ -566,7 +567,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
if not type(n.obj) in (Signal, _EdgeDetector):
self.raiseError(node, _error.UnsupportedYield)
else:
if not type(n.obj) in (Signal, _EdgeDetector, _Generator):
if not type(n.obj) in (Signal, _EdgeDetector):
self.raiseError(node, _error.UnsupportedYield)

2
myhdl/test/toVerilog/test_errors.py
View File

@ -254,7 +254,7 @@ class TestInc(TestCase):
try:
self.bench(yieldObject2)
except ToVerilogError, e:
self.assertEqual(e.kind, _error.UnsupportedYield)
self.assertEqual(e.kind, _error.NotSupported)
else:
self.fail()

32
myhdl/test/toVerilog/test_inc.py
View File

@ -27,18 +27,6 @@ def incRef(count, enable, clock, reset, n):
if enable:
count.next = (count + 1) % n
## def incTaskFunc(count, count_in, enable, clock, reset, n):
## if enable:
## count.next = (count_in + 1) % n
## def incTask(count, enable, clock, reset, n):
## while 1:
## yield posedge(clock), negedge(reset)
## if reset == ACTIVE_LOW:
## count.next = 0
## else:
## incTaskFunc(count, count, enable, clock, reset, n)
def incTask(count, enable, clock, reset, n):
def incTaskFunc(cnt, enable, reset, n):
@ -76,22 +64,7 @@ def incTaskFreeVar(count, enable, clock, reset, n):
incTaskFunc()
return incTaskGen()
def incGen(count, enable, clock, reset, n):
def gen():
yield posedge(clock), negedge(reset)
if reset == ACTIVE_LOW:
count.next = 0
else:
if enable:
count.next = (count + 1) % n
def inc():
while 1:
yield gen()
return inc()
objfile = "inc_inst.o"
analyze_cmd = "iverilog -o %s inc_inst.v tb_inc_inst.v" % objfile
@ -171,11 +144,6 @@ class TestInc(TestCase):
def testIncTaskFreeVar(self):
sim = self.bench(incTaskFreeVar)
sim.run(quiet=1)
## def testIncGen(self):
## sim = self.bench(incGen)
## sim.run(quiet=1)
if __name__ == '__main__':
unittest.main()