FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

Support for list of signals in sensitivity lists of general @instance blocks

Browse Source
This commit is contained in:
Jan Decaluwe 2008-09-10 23:04:33 +02:00
parent ebb99727b6
commit 4a8436745c
1 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
myhdl/conversion/_toVerilog.py
View File

@ -1004,14 +1004,18 @@ class _ConvertVisitor(_ConversionMixin):
def visitYield(self, node, *args):
yieldObj = self.getObj(node.value)
assert node.senslist
senslist = node.senslist
if isinstance(yieldObj, delay):
self.write("# ")
else:
self.write("@ (")
self.visit(node.value, _context.YIELD)
if isinstance(yieldObj, delay):
self.visit(node.value, _context.YIELD)
self.write(";")
else:
self.write("@ (")
for e in senslist[:-1]:
self.write(e._toVerilog())
self.write(', ')
self.write(senslist[-1]._toVerilog())
self.write(");")