from __future__ import absolute_import in all files for uniformity

myhdl/_Cosimulation.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the Cosimulation class """
+from __future__ import absolute_import
 
 
 import sys

myhdl/_ShadowSignal.py

@@ -21,6 +21,7 @@
 
 
 """
+from __future__ import absolute_import
 
 import warnings
 from copy import deepcopy

myhdl/_Signal.py

@@ -26,6 +26,7 @@ posedge -- callable to model a rising edge on a signal in a yield statement
 negedge -- callable to model a falling edge on a signal in a yield statement
 
 """
+from __future__ import absolute_import
 
 from inspect import currentframe, getouterframes
 from copy import copy, deepcopy

myhdl/_Simulation.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the Simulation class """
+from __future__ import absolute_import
 
 
 import sys

myhdl/_Waiter.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the _Waiter class """
+from __future__ import absolute_import
 
 
 from types import GeneratorType

myhdl/_always.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always function. """
+from __future__ import absolute_import
 
 
 from types import FunctionType

myhdl/_always_comb.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always_comb function. """
+from __future__ import absolute_import
 
 import sys
 import inspect

myhdl/_always_seq.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always_seq decorator. """
+from __future__ import absolute_import
 
 
 import sys

myhdl/_cell_deref.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 # cell dereferencing hack, thanks to Samuele Pedroni
 
 import new

myhdl/_concat.py

@@ -20,6 +20,7 @@
 """ module with the concat function.
 
 """
+from __future__ import absolute_import
 
 from myhdl._intbv import intbv
 from myhdl._Signal import _Signal

myhdl/_enum.py

@@ -20,6 +20,7 @@
 """ Module that implements enum.
 
 """
+from __future__ import absolute_import
 
 
 from types import StringType

myhdl/_extractHierarchy.py

@@ -20,6 +20,7 @@
 """ myhdl _extractHierarchy module.
 
 """
+from __future__ import absolute_import
 
 
 import sys

myhdl/_instance.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always function. """
+from __future__ import absolute_import
 
 
 from types import FunctionType

myhdl/_intbv.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the intbv class """
+from __future__ import absolute_import
 
 
 

myhdl/_misc.py

@@ -24,6 +24,7 @@ instances -- function that returns instances in a generator function
 downrange -- function that returns a downward range
 
 """
+from __future__ import absolute_import
 
 
 import sys

myhdl/_resolverefs.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import ast
 from types import FunctionType
 

myhdl/_traceSignals.py

@@ -20,6 +20,7 @@
 """ myhdl traceSignals module.
 
 """
+from __future__ import absolute_import
 
 
 

myhdl/_tristate.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import warnings
 
 from myhdl._Signal import _Signal, _DelayedSignal

myhdl/_unparse.py

@@ -20,6 +20,7 @@
 """ unparse module
 
 """
+from __future__ import absolute_import
 
 
 import compiler

myhdl/_util.py

@@ -20,6 +20,7 @@
 """ Module with utilility objects for MyHDL.
 
 """
+from __future__ import absolute_import
 
 
 import ast

myhdl/conversion/_analyze.py

@@ -20,6 +20,7 @@
 """ MyHDL conversion analysis module.
 
 """
+from __future__ import absolute_import
 
 import inspect
 # import compiler

myhdl/conversion/_misc.py

@@ -20,6 +20,7 @@
 """ myhdl toVerilog package.
 
 """
+from __future__ import absolute_import
 
 
 import inspect

myhdl/conversion/_toVHDL.py

@@ -20,6 +20,7 @@
 """ myhdl toVHDL conversion module.
 
 """
+from __future__ import absolute_import
 
 
 import sys

myhdl/conversion/_toVHDLPackage.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #  This file is part of the myhdl library, a Python package for using
 #  Python as a Hardware Description Language.
 #

myhdl/conversion/_toVerilog.py

@@ -20,6 +20,7 @@
 """ myhdl toVerilog conversion module.
 
 """
+from __future__ import absolute_import
 
 
 import sys

myhdl/conversion/_verify.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 import tempfile

myhdl/test/benchmark/convert.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_lfsr24 import test_lfsr24

myhdl/test/benchmark/glibc_random.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 

myhdl/test/benchmark/lfsr24.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def lfsr24(lfsr, enable, clock, reset):

myhdl/test/benchmark/long_divider.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def long_divider(

myhdl/test/benchmark/random_generator.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def random_generator(random_word, enable, clock, reset):

myhdl/test/benchmark/test_findmax.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from glibc_random import glibc_random

myhdl/test/benchmark/test_findmax_sigs.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from glibc_random import glibc_random

myhdl/test/benchmark/test_lfsr24.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from lfsr24 import lfsr24

myhdl/test/benchmark/test_longdiv.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from glibc_random import glibc_random

myhdl/test/benchmark/test_longdiv_10.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_11.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_12.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_13.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_14.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_15.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_16.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_17.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_18.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_9.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_randgen.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from random_generator import random_generator

myhdl/test/benchmark/test_timer.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from timer import timer_sig, timer_var

myhdl/test/benchmark/test_timer_array.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from timer import timer_sig, timer_var

myhdl/test/benchmark/timer.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def timer_sig(flag, clock, reset, MAXVAL):

myhdl/test/bugs/GHDL.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify
 
 verify.simulator = "GHDL"

myhdl/test/bugs/cver.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify
 
 verify.simulator = "cver"

myhdl/test/bugs/icarus.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify
 
 verify.simulator = "icarus"

myhdl/test/bugs/test_bug_1740778.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1835792.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1835797.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1837003.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error

myhdl/test/bugs/test_bug_28.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def bug_28(dout, channel):

myhdl/test/bugs/test_bug_3529686.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def bug_3529686(clr, clk, run, ack, serialout):

myhdl/test/bugs/test_bug_3577799.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_bug_39.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_42.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #! /usr/bin/env python
 
 from myhdl import *

myhdl/test/bugs/test_bug_42_2.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #! /usr/bin/env python
 
 from myhdl import *

myhdl/test/bugs/test_bug_43.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #! /usr/bin/env python
 
 from myhdl import *

myhdl/test/bugs/test_bug_44.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 WIDTH=4

myhdl/test/bugs/test_bug_aj1s.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_boolconst.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 INT_CONDITION_0 = 0 

myhdl/test/bugs/test_bug_boolop.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def gray_counter (clk, reset, enable, gray_count):

myhdl/test/bugs/test_bug_enum_toVHDL.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 #t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')

myhdl/test/bugs/test_bug_enum_toVHDL_2.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')

myhdl/test/bugs/test_issue_10.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #!/usr/bin/python2.7-32
 # -*- coding: utf-8 -*-
 

myhdl/test/bugs/test_issue_10_2.py

@@ -2,6 +2,7 @@
 # -*- coding: utf-8 -*-
 """Failed VHDL code example
 """
+from __future__ import absolute_import
 
 from myhdl import *
 from myhdl.conversion import verify

myhdl/test/bugs/test_issue_13.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_issue_9.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def issue_9():

myhdl/test/bugs/vcom.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "vcom"

myhdl/test/bugs/vlog.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "vlog"

myhdl/test/conversion/general/GHDL.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "GHDL"

myhdl/test/conversion/general/cver.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "cver"

myhdl/test/conversion/general/icarus.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "icarus"

myhdl/test/conversion/general/test_ShadowSignal.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def bench_SliceSignal():

myhdl/test/conversion/general/test_adapter.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def adapter(o_err, i_err, o_spec, i_spec):

myhdl/test/conversion/general/test_bin2gray.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_case.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def map_case4(z, a):

myhdl/test/conversion/general/test_constants.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def constants(v, u, x, y, z, a):

myhdl/test/conversion/general/test_dec.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 import random

myhdl/test/conversion/general/test_errors.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error

myhdl/test/conversion/general/test_fsm.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_hec.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange

myhdl/test/conversion/general/test_inc.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/conversion/general/test_intbv_signed.py

@@ -19,6 +19,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Run the intbv.signed() unit tests. """
+from __future__ import absolute_import
 
 from myhdl import *
 

myhdl/test/conversion/general/test_interfaces1.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 
 import sys
 

myhdl/test/conversion/general/test_interfaces2.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 
 import sys
 

myhdl/test/conversion/general/test_interfaces3.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 
 import sys
 

myhdl/test/conversion/general/test_listofsigs.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error

myhdl/test/conversion/general/test_loops.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange

myhdl/test/conversion/general/test_method.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 from myhdl import *
 from myhdl.conversion import verify

myhdl/test/conversion/general/test_nonlocal.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_numass.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from random import randrange
 
 from myhdl import *

myhdl/test/conversion/general/test_print.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error

myhdl/test/conversion/general/test_ram.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 import unittest

myhdl/test/conversion/general/test_rom.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange