diff --git a/.travis.yml b/.travis.yml index 43f2614c..573f2d44 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,6 +3,7 @@ python: - "2.6" - "2.7" - "pypy" + - "3.4" before_install: - if [ $CI_TARGET == "icarus" ]; then @@ -22,6 +23,10 @@ env: - CI_TARGET=icarus - CI_TARGET=ghdl +matrix: + allow_failures: + - python: "3.4" + script: ./ci.sh notifications: diff --git a/myhdl/_Cosimulation.py b/myhdl/_Cosimulation.py index 03c3c451..5d9544fb 100644 --- a/myhdl/_Cosimulation.py +++ b/myhdl/_Cosimulation.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the Cosimulation class """ +from __future__ import absolute_import import sys @@ -77,7 +78,7 @@ class Cosimulation(object): arglist[0] = os.path.basename(p) try: os.execvp(p, arglist) - except OSError, e: + except OSError as e: raise CosimulationError(_error.OSError, str(e)) else: os.close(wt) diff --git a/myhdl/_ShadowSignal.py b/myhdl/_ShadowSignal.py index f628248e..7f8da367 100644 --- a/myhdl/_ShadowSignal.py +++ b/myhdl/_ShadowSignal.py @@ -21,6 +21,7 @@ """ +from __future__ import absolute_import import warnings from copy import deepcopy diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py index bb823e38..b419f0ed 100644 --- a/myhdl/_Signal.py +++ b/myhdl/_Signal.py @@ -26,6 +26,8 @@ posedge -- callable to model a rising edge on a signal in a yield statement negedge -- callable to model a falling edge on a signal in a yield statement """ +from __future__ import absolute_import +from __future__ import print_function from inspect import currentframe, getouterframes from copy import copy, deepcopy @@ -295,16 +297,16 @@ class _Signal(object): # vcd print methods def _printVcdStr(self): - print >> sim._tf, "s%s %s" % (str(self._val), self._code) + print("s%s %s" % (str(self._val), self._code), file=sim._tf) def _printVcdHex(self): - print >> sim._tf, "s%s %s" % (hex(self._val), self._code) + print("s%s %s" % (hex(self._val), self._code), file=sim._tf) def _printVcdBit(self): - print >> sim._tf, "%d%s" % (self._val, self._code) + print("%d%s" % (self._val, self._code), file=sim._tf) def _printVcdVec(self): - print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code) + print("b%s %s" % (bin(self._val, self._nrbits), self._code), file=sim._tf) ### use call interface for shadow signals ### def __call__(self, left, right=None): @@ -510,14 +512,14 @@ class _Signal(object): # augmented assignment not supported def _augm(self): - raise TypeError, "Signal object doesn't support augmented assignment" + raise TypeError("Signal object doesn't support augmented assignment") __iadd__ = __isub__ = __idiv__ = __imul__ = __ipow__ = __imod__ = _augm __ior__ = __iand__ = __ixor__ = __irshift__ = __ilshift__ = _augm # index and slice assignment not supported def __setitem__(self, key, val): - raise TypeError, "Signal object doesn't support item/slice assignment" + raise TypeError("Signal object doesn't support item/slice assignment") # continues assignment support diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py index f33f110d..5527381f 100644 --- a/myhdl/_Simulation.py +++ b/myhdl/_Simulation.py @@ -18,6 +18,8 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the Simulation class """ +from __future__ import absolute_import +from __future__ import print_function import sys @@ -158,7 +160,7 @@ class Simulation(object): _futureEvents.sort() t = _simulator._time = _futureEvents[0][0] if tracing: - print >> tracefile, "#%s" % t + print("#%s" % t, file=tracefile) if cosim: cosim._put(t) while _futureEvents: @@ -188,7 +190,7 @@ class Simulation(object): self._finished = True return 0 - except Exception, e: + except Exception as e: if tracing: tracefile.flush() # if the exception came from a yield, make sure we can resume diff --git a/myhdl/_Waiter.py b/myhdl/_Waiter.py index bc6d262d..b03f6216 100644 --- a/myhdl/_Waiter.py +++ b/myhdl/_Waiter.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module that provides the _Waiter class """ +from __future__ import absolute_import from types import GeneratorType diff --git a/myhdl/__init__.py b/myhdl/__init__.py index 89909c69..0e362589 100644 --- a/myhdl/__init__.py +++ b/myhdl/__init__.py @@ -49,6 +49,8 @@ traceSignals -- function that enables signal tracing in a VCD file toVerilog -- function that converts a design to Verilog """ +from __future__ import absolute_import +from __future__ import print_function __version__ = "0.9dev" @@ -106,36 +108,36 @@ class ToVHDLWarning(ConversionWarning): # warnings.filterwarnings('always', r".*", ToVerilogWarning) def showwarning(message, category, filename, lineno, *args): - print >> sys.stderr, "** %s: %s" % (category.__name__, message) + print("** %s: %s" % (category.__name__, message), file=sys.stderr) warnings.showwarning = showwarning -from _bin import bin -from _concat import concat -from _intbv import intbv -from _modbv import modbv -from _join import join -from _Signal import posedge, negedge, Signal, SignalType -from _ShadowSignal import ConcatSignal -from _ShadowSignal import TristateSignal -from _simulator import now -from _delay import delay -from _Cosimulation import Cosimulation -from _Simulation import Simulation -from _misc import instances, downrange -from _always_comb import always_comb -from _always_seq import always_seq, ResetSignal -from _always import always -from _instance import instance -from _enum import enum, EnumType, EnumItemType -from _traceSignals import traceSignals +from ._bin import bin +from ._concat import concat +from ._intbv import intbv +from ._modbv import modbv +from ._join import join +from ._Signal import posedge, negedge, Signal, SignalType +from ._ShadowSignal import ConcatSignal +from ._ShadowSignal import TristateSignal +from ._simulator import now +from ._delay import delay +from ._Cosimulation import Cosimulation +from ._Simulation import Simulation +from ._misc import instances, downrange +from ._always_comb import always_comb +from ._always_seq import always_seq, ResetSignal +from ._always import always +from ._instance import instance +from ._enum import enum, EnumType, EnumItemType +from ._traceSignals import traceSignals from myhdl import conversion -from conversion import toVerilog -from conversion import toVHDL +from .conversion import toVerilog +from .conversion import toVHDL -from _tristate import Tristate +from ._tristate import Tristate __all__ = ["bin", diff --git a/myhdl/_always.py b/myhdl/_always.py index 343a959f..1dbe033d 100644 --- a/myhdl/_always.py +++ b/myhdl/_always.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always function. """ +from __future__ import absolute_import from types import FunctionType @@ -53,7 +54,7 @@ def always(*args): raise AlwaysError(_error.ArgType) if _isGenFunc(func): raise AlwaysError(_error.ArgType) - if func.func_code.co_argcount > 0: + if func.__code__.co_argcount > 0: raise AlwaysError(_error.NrOfArgs) return _Always(func, args) return _always_decorator diff --git a/myhdl/_always_comb.py b/myhdl/_always_comb.py index 68bdbae0..3bfbefcf 100644 --- a/myhdl/_always_comb.py +++ b/myhdl/_always_comb.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always_comb function. """ +from __future__ import absolute_import import sys import inspect @@ -47,16 +48,16 @@ def always_comb(func): raise AlwaysCombError(_error.ArgType) if _isGenFunc(func): raise AlwaysCombError(_error.ArgType) - if func.func_code.co_argcount > 0: + if func.__code__.co_argcount > 0: raise AlwaysCombError(_error.NrOfArgs) - varnames = func.func_code.co_varnames + varnames = func.__code__.co_varnames symdict = {} - for n, v in func.func_globals.items(): + for n, v in func.__globals__.items(): if n not in varnames: symdict[n] = v # handle free variables - if func.func_code.co_freevars: - for n, c in zip(func.func_code.co_freevars, func.func_closure): + if func.__code__.co_freevars: + for n, c in zip(func.__code__.co_freevars, func.__closure__): try: obj = _cell_deref(c) symdict[n] = obj diff --git a/myhdl/_always_seq.py b/myhdl/_always_seq.py index 7bca614f..bd6f87b7 100644 --- a/myhdl/_always_seq.py +++ b/myhdl/_always_seq.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always_seq decorator. """ +from __future__ import absolute_import import sys @@ -75,7 +76,7 @@ def always_seq(edge, reset): raise AlwaysSeqError(_error.ArgType) if _isGenFunc(func): raise AlwaysSeqError(_error.ArgType) - if func.func_code.co_argcount > 0: + if func.__code__.co_argcount > 0: raise AlwaysSeqError(_error.NrOfArgs) return _AlwaysSeq(func, edge, reset) return _always_seq_decorator @@ -106,14 +107,14 @@ class _AlwaysSeq(_Instantiator): # find symdict # similar to always_comb, but in class constructor - varnames = func.func_code.co_varnames + varnames = func.__code__.co_varnames symdict = {} - for n, v in func.func_globals.items(): + for n, v in func.__globals__.items(): if n not in varnames: symdict[n] = v # handle free variables - if func.func_code.co_freevars: - for n, c in zip(func.func_code.co_freevars, func.func_closure): + if func.__code__.co_freevars: + for n, c in zip(func.__code__.co_freevars, func.__closure__): try: obj = _cell_deref(c) symdict[n] = obj diff --git a/myhdl/_cell_deref.py b/myhdl/_cell_deref.py index 1c20766c..d9c6d0ed 100644 --- a/myhdl/_cell_deref.py +++ b/myhdl/_cell_deref.py @@ -1,6 +1,7 @@ + # cell dereferencing hack, thanks to Samuele Pedroni -import new +from types import FunctionType def _proto_acc(v=None): def acc(): @@ -9,10 +10,10 @@ def _proto_acc(v=None): _acc0 = _proto_acc() -_make_acc = lambda cell: (new.function (_acc0.func_code, - _acc0.func_globals, +_make_acc = lambda cell: (FunctionType(_acc0.__code__, + _acc0.__globals__, '#cell_acc', - _acc0.func_defaults, + _acc0.__defaults__, (cell,) ) ) diff --git a/myhdl/_concat.py b/myhdl/_concat.py index b39d23b1..0c758dbd 100644 --- a/myhdl/_concat.py +++ b/myhdl/_concat.py @@ -20,6 +20,7 @@ """ module with the concat function. """ +from __future__ import absolute_import from myhdl._intbv import intbv from myhdl._Signal import _Signal @@ -69,7 +70,7 @@ def concat(base, *args): raise TypeError("concat: inappropriate argument type: %s" \ % type(arg)) if not w: - raise TypeError, "concat: arg on pos %d should have length" % (i+1) + raise TypeError("concat: arg on pos %d should have length" % (i+1)) width += w val = val << w | v & (1L << w)-1 diff --git a/myhdl/_delay.py b/myhdl/_delay.py index dbd15b08..40a3f947 100644 --- a/myhdl/_delay.py +++ b/myhdl/_delay.py @@ -34,5 +34,5 @@ class delay(object): """ if not isinstance(val, (int, long)) or val < 0: - raise TypeError, _errmsg + raise TypeError(_errmsg) self._time = val diff --git a/myhdl/_enum.py b/myhdl/_enum.py index 7e3ff8ec..02bc7a3d 100644 --- a/myhdl/_enum.py +++ b/myhdl/_enum.py @@ -20,6 +20,7 @@ """ Module that implements enum. """ +from __future__ import absolute_import from types import StringType diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py index 39c1db68..1ac7cea4 100644 --- a/myhdl/_extractHierarchy.py +++ b/myhdl/_extractHierarchy.py @@ -20,6 +20,7 @@ """ myhdl _extractHierarchy module. """ +from __future__ import absolute_import import sys @@ -320,10 +321,10 @@ class _HierExtr(object): #All nested functions will be in co_consts if func: local_gens = [] - consts = func.func_code.co_consts + consts = func.__code__.co_consts for item in _flatten(arg): genfunc = _genfunc(item) - if genfunc.func_code in consts: + if genfunc.__code__ in consts: local_gens.append(item) if local_gens: objlist = _resolveRefs(symdict, local_gens) diff --git a/myhdl/_instance.py b/myhdl/_instance.py index 0285f8b3..956c4e65 100644 --- a/myhdl/_instance.py +++ b/myhdl/_instance.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the always function. """ +from __future__ import absolute_import from types import FunctionType @@ -37,7 +38,7 @@ def instance(genFunc): raise InstanceError(_error.ArgType) if not _isGenFunc(genFunc): raise InstanceError(_error.ArgType) - if genFunc.func_code.co_argcount > 0: + if genFunc.__code__.co_argcount > 0: raise InstanceError(_error.NrOfArgs) return _Instantiator(genFunc) diff --git a/myhdl/_intbv.py b/myhdl/_intbv.py index 727da4ae..4cf6f087 100644 --- a/myhdl/_intbv.py +++ b/myhdl/_intbv.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the intbv class """ +from __future__ import absolute_import @@ -113,7 +114,7 @@ class intbv(object): # iterator method def __iter__(self): if not self._nrbits: - raise TypeError, "Cannot iterate over unsized intbv" + raise TypeError("Cannot iterate over unsized intbv") return iter([self[i] for i in range(self._nrbits-1, -1, -1)]) # logical testing @@ -136,14 +137,14 @@ class intbv(object): j = 0 j = int(j) if j < 0: - raise ValueError, "intbv[i:j] requires j >= 0\n" \ - " j == %s" % j + raise ValueError("intbv[i:j] requires j >= 0\n" \ + " j == %s" % j) if i is None: # default return intbv(self._val >> j) i = int(i) if i <= j: - raise ValueError, "intbv[i:j] requires i > j\n" \ - " i, j == %s, %s" % (i, j) + raise ValueError("intbv[i:j] requires i > j\n" \ + " i, j == %s, %s" % (i, j)) res = intbv((self._val & (1L << i)-1) >> j, _nrbits=i-j) return res else: @@ -162,8 +163,8 @@ class intbv(object): j = 0 j = int(j) if j < 0: - raise ValueError, "intbv[i:j] = v requires j >= 0\n" \ - " j == %s" % j + raise ValueError("intbv[i:j] = v requires j >= 0\n" \ + " j == %s" % j) if i is None: # default q = self._val % (1L << j) self._val = val * (1L << j) + q @@ -171,12 +172,12 @@ class intbv(object): return i = int(i) if i <= j: - raise ValueError, "intbv[i:j] = v requires i > j\n" \ - " i, j, v == %s, %s, %s" % (i, j, val) + raise ValueError("intbv[i:j] = v requires i > j\n" \ + " i, j, v == %s, %s, %s" % (i, j, val)) lim = (1L << (i-j)) if val >= lim or val < -lim: - raise ValueError, "intbv[i:j] = v abs(v) too large\n" \ - " i, j, v == %s, %s, %s" % (i, j, val) + raise ValueError("intbv[i:j] = v abs(v) too large\n" \ + " i, j, v == %s, %s, %s" % (i, j, val)) mask = (lim-1) << j self._val &= ~mask self._val |= (val << j) @@ -188,8 +189,8 @@ class intbv(object): elif val == 0: self._val &= ~(1L << i) else: - raise ValueError, "intbv[i] = v requires v in (0, 1)\n" \ - " i == %s " % i + raise ValueError("intbv[i] = v requires v in (0, 1)\n" \ + " i == %s " % i) self._handleBounds() diff --git a/myhdl/_misc.py b/myhdl/_misc.py index ebd86f8e..b3f36667 100644 --- a/myhdl/_misc.py +++ b/myhdl/_misc.py @@ -24,21 +24,19 @@ instances -- function that returns instances in a generator function downrange -- function that returns a downward range """ +from __future__ import absolute_import import sys import inspect -from types import GeneratorType -from types import GeneratorType, ListType, TupleType - from myhdl._Cosimulation import Cosimulation from myhdl._instance import _Instantiator def _isGenSeq(obj): if isinstance(obj, (Cosimulation, _Instantiator)): return True - if not isinstance(obj, (ListType, TupleType, set)): + if not isinstance(obj, (list, tuple, set)): return False ## if not obj: ## return False diff --git a/myhdl/_modbv.py b/myhdl/_modbv.py index 1794ecb2..0959405d 100644 --- a/myhdl/_modbv.py +++ b/myhdl/_modbv.py @@ -18,8 +18,9 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Module with the modbv class """ +from __future__ import absolute_import -from _intbv import intbv +from ._intbv import intbv class modbv(intbv): __slots__ = [] @@ -44,14 +45,14 @@ class modbv(intbv): j = 0 j = int(j) if j < 0: - raise ValueError, "modbv[i:j] requires j >= 0\n" \ - " j == %s" % j + raise ValueError("modbv[i:j] requires j >= 0\n" \ + " j == %s" % j) if i is None: # default return modbv(self._val >> j) i = int(i) if i <= j: - raise ValueError, "modbv[i:j] requires i > j\n" \ - " i, j == %s, %s" % (i, j) + raise ValueError("modbv[i:j] requires i > j\n" \ + " i, j == %s, %s" % (i, j)) res = modbv((self._val & (1L << i)-1) >> j, _nrbits=i-j) return res else: diff --git a/myhdl/_resolverefs.py b/myhdl/_resolverefs.py index 105e3d27..b3b2e3e6 100644 --- a/myhdl/_resolverefs.py +++ b/myhdl/_resolverefs.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import ast from types import FunctionType diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py index 3dd49dd9..321ea711 100644 --- a/myhdl/_traceSignals.py +++ b/myhdl/_traceSignals.py @@ -20,6 +20,8 @@ """ myhdl traceSignals module. """ +from __future__ import absolute_import +from __future__ import print_function @@ -74,7 +76,7 @@ class _TraceSignalsClass(object): _tracing = 1 try: if self.name is None: - name = dut.func_name + name = dut.__name__ else: name = str(self.name) if name is None: @@ -118,16 +120,16 @@ def _namecode(n): return code def _writeVcdHeader(f, timescale): - print >> f, "$date" - print >> f, " %s" % time.asctime() - print >> f, "$end" - print >> f, "$version" - print >> f, " MyHDL %s" % __version__ - print >> f, "$end" - print >> f, "$timescale" - print >> f, " %s" % timescale - print >> f, "$end" - print >> f + print("$date", file=f) + print(" %s" % time.asctime(), file=f) + print("$end", file=f) + print("$version", file=f) + print(" MyHDL %s" % __version__, file=f) + print("$end", file=f) + print("$timescale", file=f) + print(" %s" % timescale, file=f) + print("$end", file=f) + print(file=f) def _writeVcdSigs(f, hierarchy, tracelists): curlevel = 0 @@ -143,8 +145,8 @@ def _writeVcdSigs(f, hierarchy, tracelists): assert(delta >= -1) if delta >= 0: for i in range(delta + 1): - print >> f, "$upscope $end" - print >> f, "$scope module %s $end" % name + print("$upscope $end", file=f) + print("$scope module %s $end" % name, file=f) for n, s in sigdict.items(): if s._val is None: raise ValueError("%s of module %s has no initial value" % (n, name)) @@ -156,11 +158,11 @@ def _writeVcdSigs(f, hierarchy, tracelists): # use real for enum strings if w and not isinstance(s._val, EnumItemType): if w == 1: - print >> f, "$var reg 1 %s %s $end" % (s._code, n) + print("$var reg 1 %s %s $end" % (s._code, n), file=f) else: - print >> f, "$var reg %s %s %s $end" % (w, s._code, n) + print("$var reg %s %s %s $end" % (w, s._code, n), file=f) else: - print >> f, "$var real 1 %s %s $end" % (s._code, n) + print("$var real 1 %s %s $end" % (s._code, n), file=f) # Memory dump by Frederik Teichert, http://teichert-ing.de, date: 2011.03.28 # The Value Change Dump standard doesn't support multidimensional arrays so # all memories are flattened and renamed. @@ -177,20 +179,20 @@ def _writeVcdSigs(f, hierarchy, tracelists): w = s._nrbits if w: if w == 1: - print >> f, "$var reg 1 %s %s(%i) $end" % (s._code, n, memindex) + print("$var reg 1 %s %s(%i) $end" % (s._code, n, memindex), file=f) else: - print >> f, "$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex) + print("$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex), file=f) else: - print >> f, "$var real 1 %s %s(%i) $end" % (s._code, n, memindex) + print("$var real 1 %s %s(%i) $end" % (s._code, n, memindex), file=f) memindex += 1 for i in range(curlevel): - print >> f, "$upscope $end" - print >> f - print >> f, "$enddefinitions $end" - print >> f, "$dumpvars" + print("$upscope $end", file=f) + print(file=f) + print("$enddefinitions $end", file=f) + print("$dumpvars", file=f) for s in siglist: s._printVcd() # initial value - print >> f, "$end" + print("$end", file=f) diff --git a/myhdl/_tristate.py b/myhdl/_tristate.py index abfce164..5a7b2ae0 100644 --- a/myhdl/_tristate.py +++ b/myhdl/_tristate.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import warnings from myhdl._Signal import _Signal, _DelayedSignal diff --git a/myhdl/_unparse.py b/myhdl/_unparse.py index f7105e69..a1eef8da 100644 --- a/myhdl/_unparse.py +++ b/myhdl/_unparse.py @@ -20,6 +20,7 @@ """ unparse module """ +from __future__ import absolute_import import compiler diff --git a/myhdl/_util.py b/myhdl/_util.py index d71f54ae..8149aa9a 100644 --- a/myhdl/_util.py +++ b/myhdl/_util.py @@ -20,6 +20,8 @@ """ Module with utilility objects for MyHDL. """ +from __future__ import absolute_import +from __future__ import print_function import ast @@ -36,7 +38,7 @@ def _printExcInfo(): # msg = msg[msg.rindex('.')+1:] if str(value): msg += ": %s" % value - print >> sys.stderr, msg + print(msg, file=sys.stderr) _isGenFunc = inspect.isgeneratorfunction diff --git a/myhdl/conversion/__init__.py b/myhdl/conversion/__init__.py index 32e7f59b..21a6264c 100644 --- a/myhdl/conversion/__init__.py +++ b/myhdl/conversion/__init__.py @@ -1,6 +1,7 @@ -from _verify import verify, analyze, registerSimulator -from _toVerilog import toVerilog -from _toVHDL import toVHDL +from __future__ import absolute_import +from ._verify import verify, analyze, registerSimulator +from ._toVerilog import toVerilog +from ._toVHDL import toVHDL __all__ = ["verify", "analyze", diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index 98284483..f9731ea7 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -20,6 +20,7 @@ """ MyHDL conversion analysis module. """ +from __future__ import absolute_import import inspect # import compiler @@ -42,7 +43,7 @@ from myhdl.conversion._misc import (_error, _access, _kind, from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode from myhdl._Signal import _Signal, _WaiterList from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal -from myhdl._util import _isTupleOfInts, _dedent +from myhdl._util import _isTupleOfInts, _dedent, _makeAST from myhdl._resolverefs import _AttrRefTransformer myhdlObjects = myhdl.__dict__.values() @@ -76,13 +77,6 @@ def _makeName(n, prefixes, namedict): ## print name return name -def _makeAST(f): - s = inspect.getsource(f) - s = _dedent(s) - tree = ast.parse(s) - tree.sourcefile = inspect.getsourcefile(f) - tree.lineoffset = inspect.getsourcelines(f)[1]-1 - return tree def _analyzeSigs(hierarchy, hdl='Verilog'): curlevel = 0 @@ -158,18 +152,13 @@ def _analyzeGens(top, absnames): tree = g elif isinstance(g, (_AlwaysComb, _AlwaysSeq, _Always)): f = g.func - s = inspect.getsource(f) - s = _dedent(s) - tree = ast.parse(s) - #print ast.dump(tree) - tree.sourcefile = inspect.getsourcefile(f) - tree.lineoffset = inspect.getsourcelines(f)[1]-1 - tree.symdict = f.func_globals.copy() + tree = _makeAST(f) + tree.symdict = f.__globals__.copy() tree.callstack = [] # handle free variables tree.nonlocaldict = {} - if f.func_code.co_freevars: - for n, c in zip(f.func_code.co_freevars, f.func_closure): + if f.__code__.co_freevars: + for n, c in zip(f.__code__.co_freevars, f.__closure__): obj = _cell_deref(c) tree.symdict[n] = obj # currently, only intbv as automatic nonlocals (until Python 3.0) @@ -189,12 +178,7 @@ def _analyzeGens(top, absnames): v.visit(tree) else: # @instance f = g.gen.gi_frame - s = inspect.getsource(f) - s = _dedent(s) - tree = ast.parse(s) - # print ast.dump(tree) - tree.sourcefile = inspect.getsourcefile(f) - tree.lineoffset = inspect.getsourcelines(f)[1]-1 + tree = _makeAST(f) tree.symdict = f.f_globals.copy() tree.symdict.update(f.f_locals) tree.nonlocaldict = {} @@ -607,24 +591,18 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): pass elif type(f) is FunctionType: argsAreInputs = False - s = inspect.getsource(f) - s = _dedent(s) - tree = ast.parse(s) - # print ast.dump(tree) - # print tree + tree = _makeAST(f) fname = f.__name__ tree.name = _Label(fname) - tree.sourcefile = inspect.getsourcefile(f) - tree.lineoffset = inspect.getsourcelines(f)[1]-1 - tree.symdict = f.func_globals.copy() + tree.symdict = f.__globals__.copy() tree.nonlocaldict = {} if fname in self.tree.callstack: self.raiseError(node, _error.NotSupported, "Recursive call") tree.callstack = self.tree.callstack[:] tree.callstack.append(fname) # handle free variables - if f.func_code.co_freevars: - for n, c in zip(f.func_code.co_freevars, f.func_closure): + if f.__code__.co_freevars: + for n, c in zip(f.__code__.co_freevars, f.__closure__): obj = _cell_deref(c) if not isinstance(obj, (int, long, _Signal)): self.raiseError(node, _error.FreeVarTypeError, n) @@ -769,7 +747,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): self.kind = _kind.DECLARATION try: self.visit(node.elt) - except ConversionError, e: + except ConversionError as e: if e.kind == _error.UnboundLocal: pass else: diff --git a/myhdl/conversion/_misc.py b/myhdl/conversion/_misc.py index 7cf10f82..3872d6a9 100644 --- a/myhdl/conversion/_misc.py +++ b/myhdl/conversion/_misc.py @@ -20,18 +20,16 @@ """ myhdl toVerilog package. """ +from __future__ import absolute_import import inspect -import compiler -from compiler import ast as astNode import ast import myhdl from myhdl import * from myhdl import ConversionError from myhdl._util import _flatten -from myhdl._unparse import _unparse class _error(object): FirstArgType = "first argument should be a classic function" diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index fef1164d..3fddfe45 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -20,6 +20,8 @@ """ myhdl toVHDL conversion module. """ +from __future__ import absolute_import +from __future__ import print_function import sys @@ -125,7 +127,7 @@ class _ToVHDLConvertor(object): _converting = 1 if self.name is None: - name = func.func_name + name = func.__name__ else: name = str(self.name) try: @@ -197,7 +199,7 @@ class _ToVHDLConvertor(object): if pfile: _writeFileHeader(pfile, ppath) - print >> pfile, _package + print(_package, file=pfile) pfile.close() _writeFileHeader(vfile, vpath) @@ -258,45 +260,45 @@ def _writeFileHeader(f, fn): date=datetime.today().ctime() ) if toVHDL.header: - print >> f, string.Template(toVHDL.header).substitute(vars) + print(string.Template(toVHDL.header).substitute(vars), file=f) if not toVHDL.no_myhdl_header: - print >> f, string.Template(myhdl_header).substitute(vars) - print >> f + print(string.Template(myhdl_header).substitute(vars), file=f) + print(file=f) def _writeCustomPackage(f, intf): - print >> f - print >> f, "package pck_%s is" % intf.name - print >> f - print >> f, "attribute enum_encoding: string;" - print >> f + print(file=f) + print("package pck_%s is" % intf.name, file=f) + print(file=f) + print("attribute enum_encoding: string;", file=f) + print(file=f) sortedList = list(_enumPortTypeSet) sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name)) for t in sortedList: - print >> f, " %s" % t._toVHDL() - print >> f - print >> f, "end package pck_%s;" % intf.name - print >> f + print(" %s" % t._toVHDL(), file=f) + print(file=f) + print("end package pck_%s;" % intf.name, file=f) + print(file=f) def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, numeric): - print >> f, "library IEEE;" - print >> f, "use IEEE.std_logic_1164.all;" - print >> f, "use IEEE.numeric_std.all;" - print >> f, "use std.textio.all;" - print >> f + print("library IEEE;", file=f) + print("use IEEE.std_logic_1164.all;", file=f) + print("use IEEE.numeric_std.all;", file=f) + print("use std.textio.all;", file=f) + print(file=f) if lib != "work": - print >> f, "library %s;" % lib + print("library %s;" % lib, file=f) if useClauses is not None: f.write(useClauses) f.write("\n") else: - print >> f, "use %s.pck_myhdl_%s.all;" % (lib, _shortversion) - print >> f + print("use %s.pck_myhdl_%s.all;" % (lib, _shortversion), file=f) + print(file=f) if needPck: - print >> f, "use %s.pck_%s.all;" % (lib, intf.name) - print >> f - print >> f, "entity %s is" % intf.name + print("use %s.pck_%s.all;" % (lib, intf.name), file=f) + print(file=f) + print("entity %s is" % intf.name, file=f) if intf.argnames: f.write(" port (") c = '' @@ -326,11 +328,11 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, numeric): ) f.write("\n %s: in %s%s" % (portname, p, r)) f.write("\n );\n") - print >> f, "end entity %s;" % intf.name - print >> f, doc - print >> f - print >> f, "architecture %s of %s is" % (arch, intf.name) - print >> f + print("end entity %s;" % intf.name, file=f) + print(doc, file=f) + print(file=f) + print("architecture %s of %s is" % (arch, intf.name), file=f) + print(file=f) def _writeFuncDecls(f): @@ -385,7 +387,7 @@ def _writeSigDecls(f, intf, siglist, memlist): ) # the following line implements initial value assignments # print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val)) - print >> f, "signal %s: %s%s;" % (s._name, p, r) + print("signal %s: %s%s;" % (s._name, p, r), file=f) elif s._read: # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) @@ -394,7 +396,7 @@ def _writeSigDecls(f, intf, siglist, memlist): category=ToVHDLWarning ) constwires.append(s) - print >> f, "signal %s: %s%s;" % (s._name, p, r) + print("signal %s: %s%s;" % (s._name, p, r), file=f) for m in memlist: if not m._used: continue @@ -409,16 +411,16 @@ def _writeSigDecls(f, intf, siglist, memlist): r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name - print >> f, "type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r) - print >> f, "signal %s: %s;" % (m.name, t) - print >> f + print("type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r), file=f) + print("signal %s: %s;" % (m.name, t), file=f) + print(file=f) def _writeCompDecls(f, compDecls): if compDecls is not None: - print >> f, compDecls + print(compDecls, file=f) def _writeModuleFooter(f, arch): - print >> f, "end architecture %s;" % arch + print("end architecture %s;" % arch, file=f) def _getRangeString(s): if isinstance(s._val, EnumItemType): @@ -469,8 +471,8 @@ def _convertGens(genlist, siglist, memlist, vfile): v = Visitor(tree, blockBuf, funcBuf) v.visit(tree) vfile.write(funcBuf.getvalue()); funcBuf.close() - print >> vfile, "begin" - print >> vfile + print("begin", file=vfile) + print(file=vfile) for s in constwires: if s._type is bool: c = int(s._val) @@ -485,19 +487,19 @@ def _convertGens(genlist, siglist, memlist, vfile): pre, suf = "to_unsigned(", ", %s)" % w else: raise ToVHDLError("Unexpected type for constant signal", s._name) - print >> vfile, "%s <= %s%s%s;" % (s._name, pre, c, suf) - print >> vfile + print("%s <= %s%s%s;" % (s._name, pre, c, suf), file=vfile) + print(file=vfile) # shadow signal assignments for s in siglist: if hasattr(s, 'toVHDL') and s._read: - print >> vfile, s.toVHDL() + print(s.toVHDL(), file=vfile) # hack for slice signals in a list for m in memlist: if m._read: for s in m.mem: if hasattr(s, 'toVHDL'): - print >> vfile, s.toVHDL() - print >> vfile + print(s.toVHDL(), file=vfile) + print(file=vfile) vfile.write(blockBuf.getvalue()); blockBuf.close() diff --git a/myhdl/conversion/_toVHDLPackage.py b/myhdl/conversion/_toVHDLPackage.py index 4d3c5259..86f7d46e 100644 --- a/myhdl/conversion/_toVHDLPackage.py +++ b/myhdl/conversion/_toVHDLPackage.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import # This file is part of the myhdl library, a Python package for using # Python as a Hardware Description Language. # diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 321c8ac0..9a65d357 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -20,6 +20,8 @@ """ myhdl toVerilog conversion module. """ +from __future__ import absolute_import +from __future__ import print_function import sys @@ -121,7 +123,7 @@ class _ToVerilogConvertor(object): _converting = 1 if self.name is None: - name = func.func_name + name = func.__name__ else: name = str(self.name) try: @@ -214,24 +216,24 @@ def _writeFileHeader(f, fn, ts): date=datetime.today().ctime() ) if not toVerilog.no_myhdl_header: - print >> f, string.Template(myhdl_header).substitute(vars) + print(string.Template(myhdl_header).substitute(vars), file=f) if toVerilog.header: - print >> f, string.Template(toVerilog.header).substitute(vars) - print >> f - print >> f, "`timescale %s" % ts - print >> f + print(string.Template(toVerilog.header).substitute(vars), file=f) + print(file=f) + print("`timescale %s" % ts, file=f) + print(file=f) def _writeModuleHeader(f, intf, doc): - print >> f, "module %s (" % intf.name + print("module %s (" % intf.name, file=f) b = StringIO() for portname in intf.argnames: - print >> b, " %s," % portname - print >> f, b.getvalue()[:-2] + print(" %s," % portname, file=b) + print(b.getvalue()[:-2], file=f) b.close() - print >> f, ");" - print >> f, doc - print >> f + print(");", file=f) + print(doc, file=f) + print(file=f) for portname in intf.argnames: s = intf.argdict[portname] if s._name is None: @@ -247,18 +249,18 @@ def _writeModuleHeader(f, intf, doc): warnings.warn("%s: %s" % (_error.OutputPortRead, portname), category=ToVerilogWarning ) - print >> f, "output %s%s%s;" % (p, r, portname) + print("output %s%s%s;" % (p, r, portname), file=f) if s._driven == 'reg': - print >> f, "reg %s%s%s;" % (p, r, portname) + print("reg %s%s%s;" % (p, r, portname), file=f) else: - print >> f, "wire %s%s%s;" % (p, r, portname) + print("wire %s%s%s;" % (p, r, portname), file=f) else: if not s._read: warnings.warn("%s: %s" % (_error.UnusedPort, portname), category=ToVerilogWarning ) - print >> f, "input %s%s%s;" % (p, r, portname) - print >> f + print("input %s%s%s;" % (p, r, portname), file=f) + print(file=f) def _writeSigDecls(f, intf, siglist, memlist): @@ -280,7 +282,7 @@ def _writeSigDecls(f, intf, siglist, memlist): k = 'reg' # the following line implements initial value assignments # print >> f, "%s %s%s = %s;" % (k, r, s._name, int(s._val)) - print >> f, "%s %s%s%s;" % (k, p, r, s._name) + print("%s %s%s%s;" % (k, p, r, s._name), file=f) elif s._read: # the original exception # raise ToVerilogError(_error.UndrivenSignal, s._name) @@ -289,8 +291,8 @@ def _writeSigDecls(f, intf, siglist, memlist): category=ToVerilogWarning ) constwires.append(s) - print >> f, "wire %s%s;" % (r, s._name) - print >> f + print("wire %s%s;" % (r, s._name), file=f) + print(file=f) for m in memlist: if not m._used: continue @@ -307,29 +309,29 @@ def _writeSigDecls(f, intf, siglist, memlist): k = 'wire' if m._driven: k = m._driven - print >> f, "%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth) - print >> f + print("%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth), file=f) + print(file=f) for s in constwires: if s._type in (bool, intbv): c = int(s.val) else: raise ToVerilogError("Unexpected type for constant signal", s._name) - print >> f, "assign %s = %s;" % (s._name, c) - print >> f + print("assign %s = %s;" % (s._name, c), file=f) + print(file=f) # shadow signal assignments for s in siglist: if hasattr(s, 'toVerilog') and s._read: - print >> f, s.toVerilog() - print >> f + print(s.toVerilog(), file=f) + print(file=f) def _writeModuleFooter(f): - print >> f, "endmodule" + print("endmodule", file=f) def _writeTestBench(f, intf, trace=False): - print >> f, "module tb_%s;" % intf.name - print >> f + print("module tb_%s;" % intf.name, file=f) + print(file=f) fr = StringIO() to = StringIO() pm = StringIO() @@ -337,32 +339,32 @@ def _writeTestBench(f, intf, trace=False): s = intf.argdict[portname] r = _getRangeString(s) if s._driven: - print >> f, "wire %s%s;" % (r, portname) - print >> to, " %s," % portname + print("wire %s%s;" % (r, portname), file=f) + print(" %s," % portname, file=to) else: - print >> f, "reg %s%s;" % (r, portname) - print >> fr, " %s," % portname - print >> pm, " %s," % portname - print >> f - print >> f, "initial begin" + print("reg %s%s;" % (r, portname), file=f) + print(" %s," % portname, file=fr) + print(" %s," % portname, file=pm) + print(file=f) + print("initial begin", file=f) if trace: - print >> f, ' $dumpfile("%s.vcd");' % intf.name - print >> f, ' $dumpvars(0, dut);' + print(' $dumpfile("%s.vcd");' % intf.name, file=f) + print(' $dumpvars(0, dut);', file=f) if fr.getvalue(): - print >> f, " $from_myhdl(" - print >> f, fr.getvalue()[:-2] - print >> f, " );" + print(" $from_myhdl(", file=f) + print(fr.getvalue()[:-2], file=f) + print(" );", file=f) if to.getvalue(): - print >> f, " $to_myhdl(" - print >> f, to.getvalue()[:-2] - print >> f, " );" - print >> f, "end" - print >> f - print >> f, "%s dut(" % intf.name - print >> f, pm.getvalue()[:-2] - print >> f, ");" - print >> f - print >> f, "endmodule" + print(" $to_myhdl(", file=f) + print(to.getvalue()[:-2], file=f) + print(" );", file=f) + print("end", file=f) + print(file=f) + print("%s dut(" % intf.name, file=f) + print(pm.getvalue()[:-2], file=f) + print(");", file=f) + print(file=f) + print("endmodule", file=f) def _getRangeString(s): diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py index ed065e2b..36f9713b 100644 --- a/myhdl/conversion/_verify.py +++ b/myhdl/conversion/_verify.py @@ -1,3 +1,5 @@ +from __future__ import absolute_import +from __future__ import print_function import sys import os import tempfile @@ -103,8 +105,8 @@ class _VerificationClass(object): def __call__(self, func, *args, **kwargs): vals = {} - vals['topname'] = func.func_name - vals['unitname'] = func.func_name.lower() + vals['topname'] = func.__name__ + vals['unitname'] = func.__name__.lower() vals['version'] = _version hdlsim = self.simulator @@ -143,11 +145,11 @@ class _VerificationClass(object): #print(analyze) ret = subprocess.call(analyze, shell=True) if ret != 0: - print >> sys.stderr, "Analysis failed" + print("Analysis failed", file=sys.stderr) return ret if self._analyzeOnly: - print >> sys.stderr, "Analysis succeeded" + print("Analysis succeeded", file=sys.stderr) return 0 f = tempfile.TemporaryFile() @@ -161,7 +163,7 @@ class _VerificationClass(object): flines = f.readlines() f.close() if not flines: - print >> sys.stderr, "No MyHDL simulation output - nothing to verify" + print("No MyHDL simulation output - nothing to verify", file=sys.stderr) return 1 @@ -169,7 +171,7 @@ class _VerificationClass(object): #print(elaborate) ret = subprocess.call(elaborate, shell=True) if ret != 0: - print >> sys.stderr, "Elaboration failed" + print("Elaboration failed", file=sys.stderr) return ret g = tempfile.TemporaryFile() @@ -214,9 +216,9 @@ class _VerificationClass(object): d.close() if not s: - print >> sys.stderr, "Conversion verification succeeded" + print("Conversion verification succeeded", file=sys.stderr) else: - print >> sys.stderr, "Conversion verification failed" + print("Conversion verification failed", file=sys.stderr) # print >> sys.stderr, s , return 1 diff --git a/myhdl/test/benchmark/convert.py b/myhdl/test/benchmark/convert.py index dbe515cb..18b0679d 100644 --- a/myhdl/test/benchmark/convert.py +++ b/myhdl/test/benchmark/convert.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_lfsr24 import test_lfsr24 diff --git a/myhdl/test/benchmark/glibc_random.py b/myhdl/test/benchmark/glibc_random.py index 044fb7f4..f27638e1 100644 --- a/myhdl/test/benchmark/glibc_random.py +++ b/myhdl/test/benchmark/glibc_random.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * diff --git a/myhdl/test/benchmark/lfsr24.py b/myhdl/test/benchmark/lfsr24.py index 2a40a5e9..83a9f91c 100644 --- a/myhdl/test/benchmark/lfsr24.py +++ b/myhdl/test/benchmark/lfsr24.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def lfsr24(lfsr, enable, clock, reset): diff --git a/myhdl/test/benchmark/long_divider.py b/myhdl/test/benchmark/long_divider.py index b9b85abe..c2b77e76 100644 --- a/myhdl/test/benchmark/long_divider.py +++ b/myhdl/test/benchmark/long_divider.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def long_divider( diff --git a/myhdl/test/benchmark/random_generator.py b/myhdl/test/benchmark/random_generator.py index 951e4ddd..46397bbb 100644 --- a/myhdl/test/benchmark/random_generator.py +++ b/myhdl/test/benchmark/random_generator.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def random_generator(random_word, enable, clock, reset): diff --git a/myhdl/test/benchmark/test_findmax.py b/myhdl/test/benchmark/test_findmax.py index 6c1b7cc3..76ef1681 100644 --- a/myhdl/test/benchmark/test_findmax.py +++ b/myhdl/test/benchmark/test_findmax.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from glibc_random import glibc_random diff --git a/myhdl/test/benchmark/test_findmax_sigs.py b/myhdl/test/benchmark/test_findmax_sigs.py index 70cd6e6c..1866815d 100644 --- a/myhdl/test/benchmark/test_findmax_sigs.py +++ b/myhdl/test/benchmark/test_findmax_sigs.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from glibc_random import glibc_random diff --git a/myhdl/test/benchmark/test_lfsr24.py b/myhdl/test/benchmark/test_lfsr24.py index b6839dd6..2c56577d 100644 --- a/myhdl/test/benchmark/test_lfsr24.py +++ b/myhdl/test/benchmark/test_lfsr24.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from lfsr24 import lfsr24 diff --git a/myhdl/test/benchmark/test_longdiv.py b/myhdl/test/benchmark/test_longdiv.py index c8145c01..734b07e4 100644 --- a/myhdl/test/benchmark/test_longdiv.py +++ b/myhdl/test/benchmark/test_longdiv.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from glibc_random import glibc_random diff --git a/myhdl/test/benchmark/test_longdiv_10.py b/myhdl/test/benchmark/test_longdiv_10.py index 94e01b64..a4feba28 100644 --- a/myhdl/test/benchmark/test_longdiv_10.py +++ b/myhdl/test/benchmark/test_longdiv_10.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_11.py b/myhdl/test/benchmark/test_longdiv_11.py index ae7ee67a..7d16807a 100644 --- a/myhdl/test/benchmark/test_longdiv_11.py +++ b/myhdl/test/benchmark/test_longdiv_11.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_12.py b/myhdl/test/benchmark/test_longdiv_12.py index 614b42ea..2c47e0d6 100644 --- a/myhdl/test/benchmark/test_longdiv_12.py +++ b/myhdl/test/benchmark/test_longdiv_12.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_13.py b/myhdl/test/benchmark/test_longdiv_13.py index 7505dbf8..d5b7cabf 100644 --- a/myhdl/test/benchmark/test_longdiv_13.py +++ b/myhdl/test/benchmark/test_longdiv_13.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_14.py b/myhdl/test/benchmark/test_longdiv_14.py index b7ed964a..9885a31c 100644 --- a/myhdl/test/benchmark/test_longdiv_14.py +++ b/myhdl/test/benchmark/test_longdiv_14.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_15.py b/myhdl/test/benchmark/test_longdiv_15.py index 256545c5..f8d208d6 100644 --- a/myhdl/test/benchmark/test_longdiv_15.py +++ b/myhdl/test/benchmark/test_longdiv_15.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_16.py b/myhdl/test/benchmark/test_longdiv_16.py index e5369513..53675553 100644 --- a/myhdl/test/benchmark/test_longdiv_16.py +++ b/myhdl/test/benchmark/test_longdiv_16.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_17.py b/myhdl/test/benchmark/test_longdiv_17.py index 3e428e5f..8709789a 100644 --- a/myhdl/test/benchmark/test_longdiv_17.py +++ b/myhdl/test/benchmark/test_longdiv_17.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_18.py b/myhdl/test/benchmark/test_longdiv_18.py index efc36183..c195f5c7 100644 --- a/myhdl/test/benchmark/test_longdiv_18.py +++ b/myhdl/test/benchmark/test_longdiv_18.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_longdiv_9.py b/myhdl/test/benchmark/test_longdiv_9.py index e479bab5..b022c474 100644 --- a/myhdl/test/benchmark/test_longdiv_9.py +++ b/myhdl/test/benchmark/test_longdiv_9.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from test_longdiv import test_longdiv diff --git a/myhdl/test/benchmark/test_randgen.py b/myhdl/test/benchmark/test_randgen.py index f07e1a0a..832f8c5a 100644 --- a/myhdl/test/benchmark/test_randgen.py +++ b/myhdl/test/benchmark/test_randgen.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from random_generator import random_generator diff --git a/myhdl/test/benchmark/test_timer.py b/myhdl/test/benchmark/test_timer.py index 5cdc2f08..70af43be 100644 --- a/myhdl/test/benchmark/test_timer.py +++ b/myhdl/test/benchmark/test_timer.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from timer import timer_sig, timer_var diff --git a/myhdl/test/benchmark/test_timer_array.py b/myhdl/test/benchmark/test_timer_array.py index 986dc23b..e6c3a9e7 100644 --- a/myhdl/test/benchmark/test_timer_array.py +++ b/myhdl/test/benchmark/test_timer_array.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from timer import timer_sig, timer_var diff --git a/myhdl/test/benchmark/timer.py b/myhdl/test/benchmark/timer.py index 82d641c9..e995476c 100644 --- a/myhdl/test/benchmark/timer.py +++ b/myhdl/test/benchmark/timer.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def timer_sig(flag, clock, reset, MAXVAL): diff --git a/myhdl/test/bugs/GHDL.py b/myhdl/test/bugs/GHDL.py index 7532ebc7..c7319a69 100644 --- a/myhdl/test/bugs/GHDL.py +++ b/myhdl/test/bugs/GHDL.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify verify.simulator = "GHDL" diff --git a/myhdl/test/bugs/cver.py b/myhdl/test/bugs/cver.py index 3b269c83..d9180915 100644 --- a/myhdl/test/bugs/cver.py +++ b/myhdl/test/bugs/cver.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify verify.simulator = "cver" diff --git a/myhdl/test/bugs/icarus.py b/myhdl/test/bugs/icarus.py index a56aeb4a..e5f596f1 100644 --- a/myhdl/test/bugs/icarus.py +++ b/myhdl/test/bugs/icarus.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify verify.simulator = "icarus" diff --git a/myhdl/test/bugs/test_bug_1740778.py b/myhdl/test/bugs/test_bug_1740778.py index abc9dfe7..ea4b2a34 100644 --- a/myhdl/test/bugs/test_bug_1740778.py +++ b/myhdl/test/bugs/test_bug_1740778.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys import os path = os.path diff --git a/myhdl/test/bugs/test_bug_1835792.py b/myhdl/test/bugs/test_bug_1835792.py index fb0cf262..a5972fc2 100644 --- a/myhdl/test/bugs/test_bug_1835792.py +++ b/myhdl/test/bugs/test_bug_1835792.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys import os path = os.path diff --git a/myhdl/test/bugs/test_bug_1835797.py b/myhdl/test/bugs/test_bug_1835797.py index c53f6681..b685f736 100644 --- a/myhdl/test/bugs/test_bug_1835797.py +++ b/myhdl/test/bugs/test_bug_1835797.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys import os path = os.path diff --git a/myhdl/test/bugs/test_bug_1837003.py b/myhdl/test/bugs/test_bug_1837003.py index f2896ab5..ad9c36e7 100644 --- a/myhdl/test/bugs/test_bug_1837003.py +++ b/myhdl/test/bugs/test_bug_1837003.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error @@ -25,7 +26,7 @@ yin = Signal(bool(0)) def test_bug_1837003(): try: toVerilog(SubFunction,xout,yout,x,y) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.ShadowingVar else: assert False diff --git a/myhdl/test/bugs/test_bug_28.py b/myhdl/test/bugs/test_bug_28.py index 98e41580..67c1cb78 100644 --- a/myhdl/test/bugs/test_bug_28.py +++ b/myhdl/test/bugs/test_bug_28.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def bug_28(dout, channel): diff --git a/myhdl/test/bugs/test_bug_3529686.py b/myhdl/test/bugs/test_bug_3529686.py index 70e63925..b820f1a4 100644 --- a/myhdl/test/bugs/test_bug_3529686.py +++ b/myhdl/test/bugs/test_bug_3529686.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def bug_3529686(clr, clk, run, ack, serialout): diff --git a/myhdl/test/bugs/test_bug_3577799.py b/myhdl/test/bugs/test_bug_3577799.py index 1dd54e97..40c09a17 100644 --- a/myhdl/test/bugs/test_bug_3577799.py +++ b/myhdl/test/bugs/test_bug_3577799.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl.conversion import analyze diff --git a/myhdl/test/bugs/test_bug_39.py b/myhdl/test/bugs/test_bug_39.py index ef6c6789..52a7307a 100644 --- a/myhdl/test/bugs/test_bug_39.py +++ b/myhdl/test/bugs/test_bug_39.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl.conversion import verify diff --git a/myhdl/test/bugs/test_bug_42.py b/myhdl/test/bugs/test_bug_42.py index bac5b875..f76be6df 100644 --- a/myhdl/test/bugs/test_bug_42.py +++ b/myhdl/test/bugs/test_bug_42.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import #! /usr/bin/env python from myhdl import * diff --git a/myhdl/test/bugs/test_bug_42_2.py b/myhdl/test/bugs/test_bug_42_2.py index eee4ba4d..a7d656b8 100644 --- a/myhdl/test/bugs/test_bug_42_2.py +++ b/myhdl/test/bugs/test_bug_42_2.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import #! /usr/bin/env python from myhdl import * diff --git a/myhdl/test/bugs/test_bug_43.py b/myhdl/test/bugs/test_bug_43.py index 9fcb2780..4f89d9b2 100644 --- a/myhdl/test/bugs/test_bug_43.py +++ b/myhdl/test/bugs/test_bug_43.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import #! /usr/bin/env python from myhdl import * diff --git a/myhdl/test/bugs/test_bug_44.py b/myhdl/test/bugs/test_bug_44.py index dea1e901..57e74207 100644 --- a/myhdl/test/bugs/test_bug_44.py +++ b/myhdl/test/bugs/test_bug_44.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * WIDTH=4 diff --git a/myhdl/test/bugs/test_bug_aj1s.py b/myhdl/test/bugs/test_bug_aj1s.py index dce4874f..850fa4b9 100644 --- a/myhdl/test/bugs/test_bug_aj1s.py +++ b/myhdl/test/bugs/test_bug_aj1s.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl.conversion import verify diff --git a/myhdl/test/bugs/test_bug_boolconst.py b/myhdl/test/bugs/test_bug_boolconst.py index f44ea223..aa867d0e 100644 --- a/myhdl/test/bugs/test_bug_boolconst.py +++ b/myhdl/test/bugs/test_bug_boolconst.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * INT_CONDITION_0 = 0 diff --git a/myhdl/test/bugs/test_bug_boolop.py b/myhdl/test/bugs/test_bug_boolop.py index 18fe76ef..2178b582 100644 --- a/myhdl/test/bugs/test_bug_boolop.py +++ b/myhdl/test/bugs/test_bug_boolop.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def gray_counter (clk, reset, enable, gray_count): diff --git a/myhdl/test/bugs/test_bug_enum_toVHDL.py b/myhdl/test/bugs/test_bug_enum_toVHDL.py index bd18b3e1..cdc06137 100644 --- a/myhdl/test/bugs/test_bug_enum_toVHDL.py +++ b/myhdl/test/bugs/test_bug_enum_toVHDL.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * #t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot') diff --git a/myhdl/test/bugs/test_bug_enum_toVHDL_2.py b/myhdl/test/bugs/test_bug_enum_toVHDL_2.py index f6bb366e..8a3d8de8 100644 --- a/myhdl/test/bugs/test_bug_enum_toVHDL_2.py +++ b/myhdl/test/bugs/test_bug_enum_toVHDL_2.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot') diff --git a/myhdl/test/bugs/test_issue_10.py b/myhdl/test/bugs/test_issue_10.py index 90cd595b..2743360f 100644 --- a/myhdl/test/bugs/test_issue_10.py +++ b/myhdl/test/bugs/test_issue_10.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import #!/usr/bin/python2.7-32 # -*- coding: utf-8 -*- diff --git a/myhdl/test/bugs/test_issue_10_2.py b/myhdl/test/bugs/test_issue_10_2.py index 7c236fb7..5ad9c176 100644 --- a/myhdl/test/bugs/test_issue_10_2.py +++ b/myhdl/test/bugs/test_issue_10_2.py @@ -2,6 +2,7 @@ # -*- coding: utf-8 -*- """Failed VHDL code example """ +from __future__ import absolute_import from myhdl import * from myhdl.conversion import verify diff --git a/myhdl/test/bugs/test_issue_13.py b/myhdl/test/bugs/test_issue_13.py index 3a0d1d5b..97aee86e 100644 --- a/myhdl/test/bugs/test_issue_13.py +++ b/myhdl/test/bugs/test_issue_13.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl.conversion import analyze diff --git a/myhdl/test/bugs/test_issue_9.py b/myhdl/test/bugs/test_issue_9.py index 9fcef7b1..25873a5a 100644 --- a/myhdl/test/bugs/test_issue_9.py +++ b/myhdl/test/bugs/test_issue_9.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def issue_9(): diff --git a/myhdl/test/bugs/vcom.py b/myhdl/test/bugs/vcom.py index bc0fb727..32f3753b 100644 --- a/myhdl/test/bugs/vcom.py +++ b/myhdl/test/bugs/vcom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "vcom" diff --git a/myhdl/test/bugs/vlog.py b/myhdl/test/bugs/vlog.py index 62ffbd67..95b433ea 100644 --- a/myhdl/test/bugs/vlog.py +++ b/myhdl/test/bugs/vlog.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "vlog" diff --git a/myhdl/test/conversion/general/GHDL.py b/myhdl/test/conversion/general/GHDL.py index 9217a30c..ea033d28 100644 --- a/myhdl/test/conversion/general/GHDL.py +++ b/myhdl/test/conversion/general/GHDL.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "GHDL" diff --git a/myhdl/test/conversion/general/cver.py b/myhdl/test/conversion/general/cver.py index 0c75ec51..98961aae 100644 --- a/myhdl/test/conversion/general/cver.py +++ b/myhdl/test/conversion/general/cver.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "cver" diff --git a/myhdl/test/conversion/general/icarus.py b/myhdl/test/conversion/general/icarus.py index 9f7a7b7d..b13985ce 100644 --- a/myhdl/test/conversion/general/icarus.py +++ b/myhdl/test/conversion/general/icarus.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "icarus" diff --git a/myhdl/test/conversion/general/test_ShadowSignal.py b/myhdl/test/conversion/general/test_ShadowSignal.py index e2cd2591..50b1ebd9 100644 --- a/myhdl/test/conversion/general/test_ShadowSignal.py +++ b/myhdl/test/conversion/general/test_ShadowSignal.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def bench_SliceSignal(): diff --git a/myhdl/test/conversion/general/test_adapter.py b/myhdl/test/conversion/general/test_adapter.py index 67d4970d..89f01599 100644 --- a/myhdl/test/conversion/general/test_adapter.py +++ b/myhdl/test/conversion/general/test_adapter.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def adapter(o_err, i_err, o_spec, i_spec): diff --git a/myhdl/test/conversion/general/test_bin2gray.py b/myhdl/test/conversion/general/test_bin2gray.py index cc337e4c..66ec04ed 100644 --- a/myhdl/test/conversion/general/test_bin2gray.py +++ b/myhdl/test/conversion/general/test_bin2gray.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path diff --git a/myhdl/test/conversion/general/test_case.py b/myhdl/test/conversion/general/test_case.py index e51ad51f..99f17628 100644 --- a/myhdl/test/conversion/general/test_case.py +++ b/myhdl/test/conversion/general/test_case.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def map_case4(z, a): diff --git a/myhdl/test/conversion/general/test_constants.py b/myhdl/test/conversion/general/test_constants.py index 172cff2c..014c9cb9 100644 --- a/myhdl/test/conversion/general/test_constants.py +++ b/myhdl/test/conversion/general/test_constants.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def constants(v, u, x, y, z, a): diff --git a/myhdl/test/conversion/general/test_dec.py b/myhdl/test/conversion/general/test_dec.py index 55a66afc..10965f09 100644 --- a/myhdl/test/conversion/general/test_dec.py +++ b/myhdl/test/conversion/general/test_dec.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import random diff --git a/myhdl/test/conversion/general/test_errors.py b/myhdl/test/conversion/general/test_errors.py index abf35298..28e60663 100644 --- a/myhdl/test/conversion/general/test_errors.py +++ b/myhdl/test/conversion/general/test_errors.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error @@ -15,7 +16,7 @@ def test_SigAugmAssignUnsupported(): a = Signal(intbv(0)[8:]) try: verify(sigAugmAssignUnsupported, z, a) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.NotSupported else: assert False @@ -34,7 +35,7 @@ def test_modbvRange(): b = Signal(intbv(0)[4:]) try: verify(modbvRange, z, a, b) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.ModbvRange else: assert False @@ -51,7 +52,7 @@ def test_modbvSigRange(): b = Signal(intbv(0)[4:]) try: verify(modbvSigRange, z, a, b) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.ModbvRange else: assert False diff --git a/myhdl/test/conversion/general/test_fsm.py b/myhdl/test/conversion/general/test_fsm.py index adf38a5d..35d6f36c 100644 --- a/myhdl/test/conversion/general/test_fsm.py +++ b/myhdl/test/conversion/general/test_fsm.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path diff --git a/myhdl/test/conversion/general/test_hec.py b/myhdl/test/conversion/general/test_hec.py index 278fa3e5..95623608 100644 --- a/myhdl/test/conversion/general/test_hec.py +++ b/myhdl/test/conversion/general/test_hec.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path from random import randrange diff --git a/myhdl/test/conversion/general/test_inc.py b/myhdl/test/conversion/general/test_inc.py index dcc96e9f..69782e29 100644 --- a/myhdl/test/conversion/general/test_inc.py +++ b/myhdl/test/conversion/general/test_inc.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys import os path = os.path diff --git a/myhdl/test/conversion/general/test_intbv_signed.py b/myhdl/test/conversion/general/test_intbv_signed.py index 8ae802f3..562d1e27 100644 --- a/myhdl/test/conversion/general/test_intbv_signed.py +++ b/myhdl/test/conversion/general/test_intbv_signed.py @@ -19,6 +19,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the intbv.signed() unit tests. """ +from __future__ import absolute_import from myhdl import * diff --git a/myhdl/test/conversion/general/test_interfaces1.py b/myhdl/test/conversion/general/test_interfaces1.py index 9f06979f..fdb6c55c 100644 --- a/myhdl/test/conversion/general/test_interfaces1.py +++ b/myhdl/test/conversion/general/test_interfaces1.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys diff --git a/myhdl/test/conversion/general/test_interfaces2.py b/myhdl/test/conversion/general/test_interfaces2.py index ce60ceef..55be2adb 100644 --- a/myhdl/test/conversion/general/test_interfaces2.py +++ b/myhdl/test/conversion/general/test_interfaces2.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys diff --git a/myhdl/test/conversion/general/test_interfaces3.py b/myhdl/test/conversion/general/test_interfaces3.py index 54243832..883f98a8 100644 --- a/myhdl/test/conversion/general/test_interfaces3.py +++ b/myhdl/test/conversion/general/test_interfaces3.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys diff --git a/myhdl/test/conversion/general/test_listofsigs.py b/myhdl/test/conversion/general/test_listofsigs.py index 6d5bd1a2..31a12624 100644 --- a/myhdl/test/conversion/general/test_listofsigs.py +++ b/myhdl/test/conversion/general/test_listofsigs.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error @@ -298,7 +299,7 @@ def test_portInList(): try: inst = conversion.analyze(portInList, z, a, b) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.PortInList else: assert False @@ -323,7 +324,7 @@ def test_sigInMultipleLists(): try: inst = conversion.analyze(sigInMultipleLists) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.SignalInMultipleLists else: assert False @@ -344,7 +345,7 @@ def test_listAsPort(): outp = [Signal(intbv(0)[8:0]) for index in range(count)] try: inst = conversion.analyze(my_register, clk, inp, outp) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.ListAsPort else: assert False diff --git a/myhdl/test/conversion/general/test_loops.py b/myhdl/test/conversion/general/test_loops.py index 5f1c7494..531f06bd 100644 --- a/myhdl/test/conversion/general/test_loops.py +++ b/myhdl/test/conversion/general/test_loops.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path from random import randrange @@ -344,7 +345,7 @@ def testWhileBreakContinueLoop(): def testForLoopError1(): try: analyze(LoopBench, ForLoopError1) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.Requirement else: assert False @@ -352,7 +353,7 @@ def testForLoopError1(): def testForLoopError2(): try: analyze(LoopBench, ForLoopError2) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.Requirement else: assert False diff --git a/myhdl/test/conversion/general/test_method.py b/myhdl/test/conversion/general/test_method.py index 535060ef..d3176025 100644 --- a/myhdl/test/conversion/general/test_method.py +++ b/myhdl/test/conversion/general/test_method.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys from myhdl import * from myhdl.conversion import verify @@ -105,7 +106,7 @@ def ObjBench(hObj): hdlobj_inst = hObj() hdl_inst = hdlobj_inst.method_func(clk, srst, x, y) else: - raise StandardError, "Incorrect hOjb %s" % (type(hObj), str(hObj)) + raise StandardError("Incorrect hOjb %s" % (type(hObj), str(hObj))) @instance diff --git a/myhdl/test/conversion/general/test_nonlocal.py b/myhdl/test/conversion/general/test_nonlocal.py index 5e36e00a..7a625e1c 100644 --- a/myhdl/test/conversion/general/test_nonlocal.py +++ b/myhdl/test/conversion/general/test_nonlocal.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path diff --git a/myhdl/test/conversion/general/test_numass.py b/myhdl/test/conversion/general/test_numass.py index 826e5e89..d8420834 100644 --- a/myhdl/test/conversion/general/test_numass.py +++ b/myhdl/test/conversion/general/test_numass.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from random import randrange from myhdl import * diff --git a/myhdl/test/conversion/general/test_print.py b/myhdl/test/conversion/general/test_print.py index 1f93e394..aacce37a 100644 --- a/myhdl/test/conversion/general/test_print.py +++ b/myhdl/test/conversion/general/test_print.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from myhdl import ConversionError from myhdl.conversion._misc import _error @@ -81,7 +82,7 @@ def PrintError1(): def testPrintError1(): try: conversion.verify(PrintError1) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.UnsupportedFormatString else: assert False @@ -97,7 +98,7 @@ def PrintError2(): def testPrintError2(): try: conversion.verify(PrintError2) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.FormatString else: assert False @@ -114,7 +115,7 @@ def PrintError3(): def testPrintError3(): try: conversion.verify(PrintError3) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.FormatString else: assert False @@ -130,7 +131,7 @@ def PrintError4(): def testPrintError4(): try: conversion.verify(PrintError4) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.UnsupportedFormatString else: assert False @@ -146,7 +147,7 @@ def PrintError5(): def testPrintError5(): try: conversion.verify(PrintError5) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.UnsupportedFormatString else: assert False diff --git a/myhdl/test/conversion/general/test_ram.py b/myhdl/test/conversion/general/test_ram.py index 95a8fc65..3d51c2e5 100644 --- a/myhdl/test/conversion/general/test_ram.py +++ b/myhdl/test/conversion/general/test_ram.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest diff --git a/myhdl/test/conversion/general/test_rom.py b/myhdl/test/conversion/general/test_rom.py index 12cae1f6..326b1959 100644 --- a/myhdl/test/conversion/general/test_rom.py +++ b/myhdl/test/conversion/general/test_rom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path from random import randrange diff --git a/myhdl/test/conversion/general/test_ternary.py b/myhdl/test/conversion/general/test_ternary.py index d4aae2a8..9871817e 100644 --- a/myhdl/test/conversion/general/test_ternary.py +++ b/myhdl/test/conversion/general/test_ternary.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest diff --git a/myhdl/test/conversion/general/test_toplevel_method.py b/myhdl/test/conversion/general/test_toplevel_method.py index 3fcc6dbd..8fd913d7 100644 --- a/myhdl/test/conversion/general/test_toplevel_method.py +++ b/myhdl/test/conversion/general/test_toplevel_method.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import sys from myhdl import * from myhdl import ConversionError @@ -120,7 +121,7 @@ def test_hdlobjnotself(): hdlobj_inst = HdlObjNotSelf() try: analyze(hdlobj_inst.method_func, clk, x, srst, y) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.NotSupported else: assert False diff --git a/myhdl/test/conversion/general/vcom.py b/myhdl/test/conversion/general/vcom.py index bc0fb727..32f3753b 100644 --- a/myhdl/test/conversion/general/vcom.py +++ b/myhdl/test/conversion/general/vcom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "vcom" diff --git a/myhdl/test/conversion/general/vlog.py b/myhdl/test/conversion/general/vlog.py index 62ffbd67..95b433ea 100644 --- a/myhdl/test/conversion/general/vlog.py +++ b/myhdl/test/conversion/general/vlog.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "vlog" diff --git a/myhdl/test/conversion/toVHDL/GHDL.py b/myhdl/test/conversion/toVHDL/GHDL.py index 7532ebc7..c7319a69 100644 --- a/myhdl/test/conversion/toVHDL/GHDL.py +++ b/myhdl/test/conversion/toVHDL/GHDL.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify verify.simulator = "GHDL" diff --git a/myhdl/test/conversion/toVHDL/test_custom.py b/myhdl/test/conversion/toVHDL/test_custom.py index 18df3ffa..0ad22592 100644 --- a/myhdl/test/conversion/toVHDL/test_custom.py +++ b/myhdl/test/conversion/toVHDL/test_custom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path @@ -259,7 +260,7 @@ def testInc3(): def testIncGen(): try: assert conversion.verify(customBench, incGen) == 0 - except ConversionError, e: + except ConversionError as e: pass else: assert False @@ -267,7 +268,7 @@ def testIncGen(): def testIncErr(): try: assert conversion.verify(customBench, incErr) == 0 - except ConversionError, e: + except ConversionError as e: pass else: assert False diff --git a/myhdl/test/conversion/toVHDL/test_enum.py b/myhdl/test/conversion/toVHDL/test_enum.py index d286849b..a715c0a0 100644 --- a/myhdl/test/conversion/toVHDL/test_enum.py +++ b/myhdl/test/conversion/toVHDL/test_enum.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from random import randrange diff --git a/myhdl/test/conversion/toVHDL/test_loops.py b/myhdl/test/conversion/toVHDL/test_loops.py index 706e147b..ec111995 100644 --- a/myhdl/test/conversion/toVHDL/test_loops.py +++ b/myhdl/test/conversion/toVHDL/test_loops.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path from random import randrange @@ -41,7 +42,7 @@ def LoopBench(LoopTest): def testForLoopError1(): try: analyze(LoopBench, ForLoopError1) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.Requirement else: assert False diff --git a/myhdl/test/conversion/toVHDL/test_newcustom.py b/myhdl/test/conversion/toVHDL/test_newcustom.py index c7e6db1d..2c1a123f 100644 --- a/myhdl/test/conversion/toVHDL/test_newcustom.py +++ b/myhdl/test/conversion/toVHDL/test_newcustom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path @@ -259,7 +260,7 @@ def testInc3(): def testIncGen(): try: assert conversion.verify(customBench, incGen) == 0 - except ConversionError, e: + except ConversionError as e: pass else: assert False @@ -267,7 +268,7 @@ def testIncGen(): def testIncErr(): try: assert conversion.verify(customBench, incErr) == 0 - except ConversionError, e: + except ConversionError as e: pass else: assert False diff --git a/myhdl/test/conversion/toVHDL/test_ops.py b/myhdl/test/conversion/toVHDL/test_ops.py index dba639a3..5badb0f6 100644 --- a/myhdl/test/conversion/toVHDL/test_ops.py +++ b/myhdl/test/conversion/toVHDL/test_ops.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import random diff --git a/myhdl/test/conversion/toVHDL/test_signed.py b/myhdl/test/conversion/toVHDL/test_signed.py index 49e9af9a..4bfdef3f 100644 --- a/myhdl/test/conversion/toVHDL/test_signed.py +++ b/myhdl/test/conversion/toVHDL/test_signed.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import random diff --git a/myhdl/test/conversion/toVHDL/vcom.py b/myhdl/test/conversion/toVHDL/vcom.py index bc0fb727..32f3753b 100644 --- a/myhdl/test/conversion/toVHDL/vcom.py +++ b/myhdl/test/conversion/toVHDL/vcom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "vcom" diff --git a/myhdl/test/conversion/toVerilog/test_GrayInc.py b/myhdl/test/conversion/toVerilog/test_GrayInc.py index 4aef6ad1..536c8593 100644 --- a/myhdl/test/conversion/toVerilog/test_GrayInc.py +++ b/myhdl/test/conversion/toVerilog/test_GrayInc.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -75,7 +76,7 @@ class TestGrayInc(unittest.TestCase): def bench(self): gray_inc_reg_1 = toVerilog(GrayIncReg, graycnt, enable, clock, reset, width) - gray_inc_reg_v = GrayIncReg_v(GrayIncReg.func_name, graycnt_v, enable, clock, reset, width) + gray_inc_reg_v = GrayIncReg_v(GrayIncReg.__name__, graycnt_v, enable, clock, reset, width) clk_1 = self.clockGen() st_1 = self.stimulus() ch_1 = self.check() diff --git a/myhdl/test/conversion/toVerilog/test_NotSupported.py b/myhdl/test/conversion/toVerilog/test_NotSupported.py index 13a12ae1..35663b4b 100644 --- a/myhdl/test/conversion/toVerilog/test_NotSupported.py +++ b/myhdl/test/conversion/toVerilog/test_NotSupported.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -11,7 +12,7 @@ class TestNotSupported(unittest.TestCase): def check(self, *args): try: i = toVerilog(*args) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) except: self.fail() diff --git a/myhdl/test/conversion/toVerilog/test_RandomScrambler.py b/myhdl/test/conversion/toVerilog/test_RandomScrambler.py index e12ab252..7a73f523 100644 --- a/myhdl/test/conversion/toVerilog/test_RandomScrambler.py +++ b/myhdl/test/conversion/toVerilog/test_RandomScrambler.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -123,7 +124,7 @@ class TestRandomScrambler(TestCase): i7, i6, i5, i4, i3, i2, i1, i0 ) # time.sleep(1) - rs_v = RandomScrambler_v(RandomScrambler.func_name, + rs_v = RandomScrambler_v(RandomScrambler.__name__, v7, v6, v5, v4, v3, v2, v1, v0, i7, i6, i5, i4, i3, i2, i1, i0 ) diff --git a/myhdl/test/conversion/toVerilog/test_all.py b/myhdl/test/conversion/toVerilog/test_all.py index 2742c5a0..651365e0 100644 --- a/myhdl/test/conversion/toVerilog/test_all.py +++ b/myhdl/test/conversion/toVerilog/test_all.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run all myhdl toVerilog unit tests. """ +from __future__ import absolute_import import os diff --git a/myhdl/test/conversion/toVerilog/test_always_comb.py b/myhdl/test/conversion/toVerilog/test_always_comb.py index 49698b77..848e05a8 100644 --- a/myhdl/test/conversion/toVerilog/test_always_comb.py +++ b/myhdl/test/conversion/toVerilog/test_always_comb.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for always_comb """ +from __future__ import absolute_import import random @@ -97,7 +98,7 @@ class AlwaysCombSimulationTest(TestCase): random.shuffle(vectors) design_inst = toVerilog(design, a, b, c, d, p, q, r) - design_v_inst = design_v(design.func_name, a, b, c, d, p_v, q_v, r_v) + design_v_inst = design_v(design.__name__, a, b, c, d, p_v, q_v, r_v) def clkGen(): while 1: @@ -118,7 +119,7 @@ class AlwaysCombSimulationTest(TestCase): self.assertEqual(q, q_v) self.assertEqual(r, r_v) - raise StopSimulation, "always_comb simulation test" + raise StopSimulation("always_comb simulation test") return design_inst, design_v_inst, clkGen(), stimulus() diff --git a/myhdl/test/conversion/toVerilog/test_beh.py b/myhdl/test/conversion/toVerilog/test_beh.py index 4a785447..bc17b83d 100644 --- a/myhdl/test/conversion/toVerilog/test_beh.py +++ b/myhdl/test/conversion/toVerilog/test_beh.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -82,7 +83,7 @@ class TestBeh(TestCase): beh_inst = toVerilog(beh, count, enable, clock, reset, n=n) # beh_inst = beh(count, enable, clock, reset, n=n) - beh_inst_v = beh_v(beh.func_name, count_v, enable, clock, reset) + beh_inst_v = beh_v(beh.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_bin2gray.py b/myhdl/test/conversion/toVerilog/test_bin2gray.py index 1dd6fe29..d85ce15f 100644 --- a/myhdl/test/conversion/toVerilog/test_bin2gray.py +++ b/myhdl/test/conversion/toVerilog/test_bin2gray.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -69,7 +70,7 @@ class TestBin2Gray(TestCase): bin2gray_inst = toVerilog(bin2gray, B, G, width) # bin2gray_inst = bin2gray(B, G, width) - bin2gray_v_inst = bin2gray_v(bin2gray.func_name, B, G_v) + bin2gray_v_inst = bin2gray_v(bin2gray.__name__, B, G_v) def stimulus(): for i in range(2**width): diff --git a/myhdl/test/conversion/toVerilog/test_bugreports.py b/myhdl/test/conversion/toVerilog/test_bugreports.py index ce5cb03c..1bacb196 100644 --- a/myhdl/test/conversion/toVerilog/test_bugreports.py +++ b/myhdl/test/conversion/toVerilog/test_bugreports.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * from util import verilogCompile @@ -35,7 +36,7 @@ def test(): x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)] toVerilog(TestModule, x,a,b,c,d,e) - verilogCompile(TestModule.func_name) + verilogCompile(TestModule.__name__) test() @@ -78,7 +79,7 @@ def test(): x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)] toVerilog(TestModule, x,a,b,c,d,e) - verilogCompile(TestModule.func_name) + verilogCompile(TestModule.__name__) test() @@ -110,7 +111,7 @@ def test(): SOF = Signal(bool(0)) toVerilog(top, SOF, clk, reset_n) - verilogCompile(top.func_name) + verilogCompile(top.__name__) test() diff --git a/myhdl/test/conversion/toVerilog/test_custom.py b/myhdl/test/conversion/toVerilog/test_custom.py index 193911f4..8742f3d4 100644 --- a/myhdl/test/conversion/toVerilog/test_custom.py +++ b/myhdl/test/conversion/toVerilog/test_custom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -234,7 +235,7 @@ class TestInc(TestCase): inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(incVer, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) - inc_inst_v = inc_v(incVer.func_name, count_v, enable, clock, reset) + inc_inst_v = inc_v(incVer.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) @@ -271,7 +272,7 @@ class TestInc(TestCase): clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incGen, count_v, enable, clock, reset, n=n) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -284,7 +285,7 @@ class TestInc(TestCase): clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incErr, count_v, enable, clock, reset, n=n) - except ConversionError, e: + except ConversionError as e: pass else: self.fail() diff --git a/myhdl/test/conversion/toVerilog/test_dec.py b/myhdl/test/conversion/toVerilog/test_dec.py index 597bb17f..6032f43f 100644 --- a/myhdl/test/conversion/toVerilog/test_dec.py +++ b/myhdl/test/conversion/toVerilog/test_dec.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -182,7 +183,7 @@ class TestDec(TestCase): dec_inst_ref = decRef(count, enable, clock, reset, n=n) dec_inst = toVerilog(dec, count, enable, clock, reset, n=n) # dec_inst = dec(count, enable, clock, reset, n=n) - dec_inst_v = dec_v(dec.func_name, count_v, enable, clock, reset) + dec_inst_v = dec_v(dec.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_edge.py b/myhdl/test/conversion/toVerilog/test_edge.py index f624f459..bdd4a0fa 100644 --- a/myhdl/test/conversion/toVerilog/test_edge.py +++ b/myhdl/test/conversion/toVerilog/test_edge.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -100,7 +101,7 @@ class TestEdge(TestCase): self.assertEqual(flag, expected) edge_inst = toVerilog(edge, flag, sig, clock) - edge_inst_v = edge_v(edge.func_name, flag, sig, clock) + edge_inst_v = edge_v(edge.__name__, flag, sig, clock) return clockgen, stimulus, delayline, check, edge_inst_v diff --git a/myhdl/test/conversion/toVerilog/test_errors.py b/myhdl/test/conversion/toVerilog/test_errors.py index 0781e321..f5cf1b66 100644 --- a/myhdl/test/conversion/toVerilog/test_errors.py +++ b/myhdl/test/conversion/toVerilog/test_errors.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -357,7 +358,7 @@ class TestErr(TestCase): def testInternalSignal(self): try: self.bench(internalSignal) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.TypeInfer) else: self.fail() @@ -365,7 +366,7 @@ class TestErr(TestCase): def testMultipleDrivenSignal(self): try: self.bench(multipleDrivenSignal) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.SigMultipleDriven) else: self.fail() @@ -373,7 +374,7 @@ class TestErr(TestCase): def testShadowingSignal(self): try: self.bench(shadowingSignal) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.ShadowingSignal) else: self.fail() @@ -381,7 +382,7 @@ class TestErr(TestCase): def testUndefinedBitWidthSignal(self): try: self.bench(undefinedBitWidthSignal) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.UndefinedBitWidth) else: self.fail() @@ -389,7 +390,7 @@ class TestErr(TestCase): def testFreeVarTypeError(self): try: self.bench(freeVarTypeError) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.FreeVarTypeError) else: self.fail() @@ -405,7 +406,7 @@ class TestErr(TestCase): def testYield1(self): try: self.bench(yieldObject1) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedYield) else: self.fail() @@ -413,7 +414,7 @@ class TestErr(TestCase): def testYield2(self): try: self.bench(yieldObject2) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -421,7 +422,7 @@ class TestErr(TestCase): def testRecursion1(self): try: self.bench(recursion1) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -429,7 +430,7 @@ class TestErr(TestCase): def testRecursion2(self): try: self.bench(recursion2) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -437,7 +438,7 @@ class TestErr(TestCase): def testFunctionNoReturnVal(self): try: self.bench(functionNoReturnVal) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -445,7 +446,7 @@ class TestErr(TestCase): def testTaskReturnVal(self): try: self.bench(taskReturnVal) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -453,7 +454,7 @@ class TestErr(TestCase): def testPrintnlToFile(self): try: self.bench(printnlToFile) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -461,7 +462,7 @@ class TestErr(TestCase): def testPrintToFile(self): try: self.bench(printToFile) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -469,7 +470,7 @@ class TestErr(TestCase): def testListComp1(self): try: self.bench(listComp1) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -477,7 +478,7 @@ class TestErr(TestCase): def testListComp2(self): try: self.bench(listComp2) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() @@ -485,7 +486,7 @@ class TestErr(TestCase): def testListComp3(self): try: self.bench(listComp3) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() @@ -493,7 +494,7 @@ class TestErr(TestCase): def testListComp4(self): try: self.bench(listComp4) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() @@ -501,7 +502,7 @@ class TestErr(TestCase): def testListComp5(self): try: self.bench(listComp5) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.UnsupportedListComp) else: self.fail() @@ -509,7 +510,7 @@ class TestErr(TestCase): def testUndefinedBitWidthMem(self): try: self.bench(undefinedBitWidthMem) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.UndefinedBitWidth) else: self.fail() @@ -517,7 +518,7 @@ class TestErr(TestCase): def testInconsistentTypeMem(self): try: self.bench(inconsistentTypeMem) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.InconsistentType) else: self.fail() @@ -525,7 +526,7 @@ class TestErr(TestCase): def testInconsistentBitWidthMem(self): try: self.bench(inconsistentBitWidthMem) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.InconsistentBitWidth) else: self.fail() diff --git a/myhdl/test/conversion/toVerilog/test_fsm.py b/myhdl/test/conversion/toVerilog/test_fsm.py index 5607e481..9c954cb1 100644 --- a/myhdl/test/conversion/toVerilog/test_fsm.py +++ b/myhdl/test/conversion/toVerilog/test_fsm.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -173,7 +174,7 @@ class FramerCtrlTest(TestCase): framerctrl_ref_inst = FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State) framerctrl_inst = toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n, t_State) - framerctrl_v_inst = FramerCtrl_v(FramerCtrl.func_name, + framerctrl_v_inst = FramerCtrl_v(FramerCtrl.__name__, SOF_v, state_v, syncFlag, clk, reset_n) def clkgen(): diff --git a/myhdl/test/conversion/toVerilog/test_hec.py b/myhdl/test/conversion/toVerilog/test_hec.py index 5982b941..eddf2fde 100644 --- a/myhdl/test/conversion/toVerilog/test_hec.py +++ b/myhdl/test/conversion/toVerilog/test_hec.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -144,7 +145,7 @@ class TestHec(unittest.TestCase): heccalc_inst = toVerilog(HecCalculator, hec, header) # heccalc_inst = HecCalculator(hec, header) - heccalc_v_inst = HecCalculator_v(HecCalculator.func_name, hec_v, header) + heccalc_v_inst = HecCalculator_v(HecCalculator.__name__, hec_v, header) def stimulus(): for h in headers: diff --git a/myhdl/test/conversion/toVerilog/test_inc.py b/myhdl/test/conversion/toVerilog/test_inc.py index 8843a55c..516c9eed 100644 --- a/myhdl/test/conversion/toVerilog/test_inc.py +++ b/myhdl/test/conversion/toVerilog/test_inc.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -159,7 +160,7 @@ class TestInc(TestCase): inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(inc, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) - inc_inst_v = inc_v(inc.func_name, count_v, enable, clock, reset) + inc_inst_v = inc_v(inc.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_inc_initial.py b/myhdl/test/conversion/toVerilog/test_inc_initial.py index 7ac74578..cca2367b 100644 --- a/myhdl/test/conversion/toVerilog/test_inc_initial.py +++ b/myhdl/test/conversion/toVerilog/test_inc_initial.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -87,8 +88,8 @@ class TestInc_initial(TestCase): count_v = Signal(intbv(0)[m:]) enable, clock, reset = [Signal(bool()) for i in range(3)] - inc_initial_1 = toVerilog(top, top.func_name, count, enable, clock, reset, n=n) - inc_initial_v = top(top.func_name, count_v, enable, clock, reset, n=n, arch='verilog') + inc_initial_1 = toVerilog(top, top.__name__, count, enable, clock, reset, n=n) + inc_initial_v = top(top.__name__, count_v, enable, clock, reset, n=n, arch='verilog') clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_infer.py b/myhdl/test/conversion/toVerilog/test_infer.py index 119d3b9c..9eec891d 100644 --- a/myhdl/test/conversion/toVerilog/test_infer.py +++ b/myhdl/test/conversion/toVerilog/test_infer.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -138,7 +139,7 @@ class TestErrors(unittest.TestCase): def check(self, *args): try: i = toVerilog(*args) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) except: self.fail() @@ -151,7 +152,7 @@ class TestErrors(unittest.TestCase): out = Signal(intbv(0)[16:]) try: infertest_inst = toVerilog(Infertest, a, out) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, err) except: self.fail() @@ -295,7 +296,7 @@ class TestInfer(unittest.TestCase): infertest_inst = toVerilog(Infertest, a, out) # infertest_inst = Infertest(hec, header) - infertest_v_inst = Infertest_v(Infertest.func_name, a, out_v) + infertest_v_inst = Infertest_v(Infertest.__name__, a, out_v) def stimulus(): a.next = 1 diff --git a/myhdl/test/conversion/toVerilog/test_loops.py b/myhdl/test/conversion/toVerilog/test_loops.py index 09f8e160..e88e2eb8 100644 --- a/myhdl/test/conversion/toVerilog/test_loops.py +++ b/myhdl/test/conversion/toVerilog/test_loops.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -265,7 +266,7 @@ class TestLoops(unittest.TestCase): looptest_inst = toVerilog(LoopTest, a, out) # looptest_inst = LoopTest(hec, header) - looptest_v_inst = LoopTest_v(LoopTest.func_name, a, out_v) + looptest_v_inst = LoopTest_v(LoopTest.__name__, a, out_v) def stimulus(): for i in range(100): diff --git a/myhdl/test/conversion/toVerilog/test_misc.py b/myhdl/test/conversion/toVerilog/test_misc.py index a59a5abe..a233872f 100644 --- a/myhdl/test/conversion/toVerilog/test_misc.py +++ b/myhdl/test/conversion/toVerilog/test_misc.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import unittest import os path = os.path @@ -57,7 +58,7 @@ class TestConstWires(unittest.TestCase): q_v = Signal(bool(0)) constwire_inst = toVerilog(ConstWire, p, q) - constwire_v_inst = ConstWire_v(ConstWire.func_name, p, q_v) + constwire_v_inst = ConstWire_v(ConstWire.__name__, p, q_v) def stimulus(): for i in range(100): @@ -82,7 +83,7 @@ class TestConstWires(unittest.TestCase): q_v = Signal(intbv(0)[8:]) constwire_inst = toVerilog(ConstWire, p, q) - constwire_v_inst = ConstWire_v(ConstWire.func_name, p, q_v) + constwire_v_inst = ConstWire_v(ConstWire.__name__, p, q_v) def stimulus(): for i in range(100): @@ -132,7 +133,7 @@ class TestIgnoreCode(unittest.TestCase): ignorecode_inst = toVerilog(adder, a, b, c) # ignorecode_inst = adder(a, b, c) - ignorecode_v_inst = Ignorecode_v(adder.func_name, a, b, c_v) + ignorecode_v_inst = Ignorecode_v(adder.__name__, a, b, c_v) def stimulus(): for i in range(100): diff --git a/myhdl/test/conversion/toVerilog/test_newcustom.py b/myhdl/test/conversion/toVerilog/test_newcustom.py index a22204ad..13695fe2 100644 --- a/myhdl/test/conversion/toVerilog/test_newcustom.py +++ b/myhdl/test/conversion/toVerilog/test_newcustom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -234,7 +235,7 @@ class TestInc(TestCase): inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(incVer, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) - inc_inst_v = inc_v(incVer.func_name, count_v, enable, clock, reset) + inc_inst_v = inc_v(incVer.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) @@ -271,7 +272,7 @@ class TestInc(TestCase): clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incGen, count_v, enable, clock, reset, n=n) - except ConversionError, e: + except ConversionError as e: self.assertEqual(e.kind, _error.NotSupported) else: self.fail() @@ -284,7 +285,7 @@ class TestInc(TestCase): clock, reset = [Signal(bool()) for i in range(2)] try: inc_inst = toVerilog(incErr, count_v, enable, clock, reset, n=n) - except ConversionError, e: + except ConversionError as e: pass else: self.fail() diff --git a/myhdl/test/conversion/toVerilog/test_ops.py b/myhdl/test/conversion/toVerilog/test_ops.py index afacb861..79803ec0 100644 --- a/myhdl/test/conversion/toVerilog/test_ops.py +++ b/myhdl/test/conversion/toVerilog/test_ops.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -146,7 +147,7 @@ class TestBinaryOps(TestCase): And, Or, left, right) - binops_v = binaryOps_v(binaryOps.func_name, + binops_v = binaryOps_v(binaryOps.__name__, Bitand_v, Bitor_v, Bitxor_v, @@ -274,7 +275,7 @@ class TestMultiOps(TestCase): And, Or, argm, argn, argp) - multiops_v = multiOps_v(multiOps.func_name, + multiops_v = multiOps_v(multiOps.__name__, Bitand_v, Bitor_v, Bitxor_v, @@ -371,7 +372,7 @@ class TestUnaryOps(TestCase): UnaryAdd, UnarySub, arg) - unaryops_v = unaryOps_v(unaryOps.func_name, + unaryops_v = unaryOps_v(unaryOps.__name__, Not_v, Invert_v, UnaryAdd_v, @@ -514,7 +515,7 @@ class TestAugmOps(TestCase): Sub, Sum, left, right) - augmops_v = augmOps_v( augmOps.func_name, + augmops_v = augmOps_v( augmOps.__name__, Bitand_v, Bitor_v, Bitxor_v, diff --git a/myhdl/test/conversion/toVerilog/test_ram.py b/myhdl/test/conversion/toVerilog/test_ram.py index 2f9d21b7..7bc6fb94 100644 --- a/myhdl/test/conversion/toVerilog/test_ram.py +++ b/myhdl/test/conversion/toVerilog/test_ram.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -115,7 +116,7 @@ class TestMemory(TestCase): # mem_inst = ram(dout, din, addr, we, clk, depth) mem_inst = toVerilog(ram, dout, din, addr, we, clk, depth) - mem_v_inst = ram_v(ram.func_name, dout_v, din, addr, we, clk, depth) + mem_v_inst = ram_v(ram.__name__, dout_v, din, addr, we, clk, depth) def stimulus(): for i in range(depth): diff --git a/myhdl/test/conversion/toVerilog/test_rom.py b/myhdl/test/conversion/toVerilog/test_rom.py index a1dfd3ac..13343f95 100644 --- a/myhdl/test/conversion/toVerilog/test_rom.py +++ b/myhdl/test/conversion/toVerilog/test_rom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -71,7 +72,7 @@ class TestRom(TestCase): # rom_inst = rom(dout, din, addr, we, clk, depth) rom_inst = toVerilog(rom, dout, addr, clk) - rom_v_inst = rom_v(rom.func_name, dout_v, addr, clk) + rom_v_inst = rom_v(rom.__name__, dout_v, addr, clk) def stimulus(): for i in range(D): diff --git a/myhdl/test/conversion/toVerilog/test_signed.py b/myhdl/test/conversion/toVerilog/test_signed.py index 1078abc9..e14f73fc 100644 --- a/myhdl/test/conversion/toVerilog/test_signed.py +++ b/myhdl/test/conversion/toVerilog/test_signed.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import unittest @@ -150,7 +151,7 @@ class TestBinaryOps(TestCase): And, Or, left, right, bit) - binops_v = binaryOps_v(binaryOps.func_name, + binops_v = binaryOps_v(binaryOps.__name__, ## Bitand_v, ## Bitor_v, ## Bitxor_v, @@ -295,7 +296,7 @@ class TestUnaryOps(TestCase): UnaryAdd, UnarySub, arg) - unaryops_v = unaryOps_v(unaryOps.func_name, + unaryops_v = unaryOps_v(unaryOps.__name__, Not_v, Invert_v, UnaryAdd_v, @@ -448,7 +449,7 @@ class TestAugmOps(TestCase): Sub, Sum, left, right) - augmops_v = augmOps_v( augmOps.func_name, + augmops_v = augmOps_v( augmOps.__name__, ## Bitand_v, ## Bitor_v, ## Bitxor_v, diff --git a/myhdl/test/conversion/toVerilog/util.py b/myhdl/test/conversion/toVerilog/util.py index 658f6a92..b90fd8a7 100644 --- a/myhdl/test/conversion/toVerilog/util.py +++ b/myhdl/test/conversion/toVerilog/util.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path import subprocess diff --git a/myhdl/test/conversion/toVerilog2/cver.py b/myhdl/test/conversion/toVerilog2/cver.py index 0c75ec51..98961aae 100644 --- a/myhdl/test/conversion/toVerilog2/cver.py +++ b/myhdl/test/conversion/toVerilog2/cver.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "cver" diff --git a/myhdl/test/conversion/toVerilog2/icarus.py b/myhdl/test/conversion/toVerilog2/icarus.py index 9f7a7b7d..b13985ce 100644 --- a/myhdl/test/conversion/toVerilog2/icarus.py +++ b/myhdl/test/conversion/toVerilog2/icarus.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "icarus" diff --git a/myhdl/test/conversion/toVerilog2/test_loops.py b/myhdl/test/conversion/toVerilog2/test_loops.py index 63475c12..201e90d2 100644 --- a/myhdl/test/conversion/toVerilog2/test_loops.py +++ b/myhdl/test/conversion/toVerilog2/test_loops.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import import os path = os.path from random import randrange @@ -40,7 +41,7 @@ def LoopBench(LoopTest): def testForLoopError1(): try: analyze(LoopBench, ForLoopError1) - except ConversionError, e: + except ConversionError as e: assert e.kind == _error.Requirement else: assert False diff --git a/myhdl/test/conversion/toVerilog2/vcom.py b/myhdl/test/conversion/toVerilog2/vcom.py index bc0fb727..32f3753b 100644 --- a/myhdl/test/conversion/toVerilog2/vcom.py +++ b/myhdl/test/conversion/toVerilog2/vcom.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "vcom" diff --git a/myhdl/test/conversion/toVerilog2/vlog.py b/myhdl/test/conversion/toVerilog2/vlog.py index 62ffbd67..95b433ea 100644 --- a/myhdl/test/conversion/toVerilog2/vlog.py +++ b/myhdl/test/conversion/toVerilog2/vlog.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl.conversion import verify, analyze verify.simulator = analyze.simulator = "vlog" diff --git a/myhdl/test/core/perf_inferWaiter.py b/myhdl/test/core/perf_inferWaiter.py index b5840127..b0fdd2bd 100644 --- a/myhdl/test/core/perf_inferWaiter.py +++ b/myhdl/test/core/perf_inferWaiter.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for inferWaiter """ +from __future__ import absolute_import import random diff --git a/myhdl/test/core/test_Cosimulation.py b/myhdl/test/core/test_Cosimulation.py index 97896a89..3cbbe2f5 100644 --- a/myhdl/test/core/test_Cosimulation.py +++ b/myhdl/test/core/test_Cosimulation.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run unit tests for Cosimulation """ +from __future__ import absolute_import import sys @@ -58,8 +59,8 @@ class CosimulationTest(TestCase): def testWrongExe(self): try: Cosimulation("bla -x 45") - except CosimulationError, e: - self.assert_(e.kind in(_error.OSError, _error.SimulationEnd)) + except CosimulationError as e: + self.assertTrue(e.kind in(_error.OSError, _error.SimulationEnd)) else: self.fail() @@ -67,7 +68,7 @@ class CosimulationTest(TestCase): cosim1 = Cosimulation(exe + ".cosimNotUnique", **allSigs) try: Cosimulation(exe + ".cosimNotUnique", **allSigs) - except CosimulationError, e: + except CosimulationError as e: self.assertEqual(e.kind, _error.MultipleCosim) else: self.fail() @@ -146,7 +147,7 @@ class CosimulationTest(TestCase): def testTimeZero(self): try: Cosimulation(exe + ".cosimTimeZero", **allSigs) - except CosimulationError, e: + except CosimulationError as e: self.assertEqual(e.kind, _error.TimeZero) except: self.fail() @@ -162,7 +163,7 @@ class CosimulationTest(TestCase): def testNoComm(self): try: Cosimulation(exe + ".cosimNoComm", **allSigs) - except CosimulationError, e: + except CosimulationError as e: self.assertEqual(e.kind, _error.NoCommunication) else: self.fail() @@ -180,7 +181,7 @@ class CosimulationTest(TestCase): def testFromSignalsDupl(self): try: Cosimulation(exe + ".cosimFromSignalsDupl", **allSigs) - except CosimulationError, e: + except CosimulationError as e: self.assertEqual(e.kind, _error.DuplicateSigNames) else: self.fail() @@ -197,7 +198,7 @@ class CosimulationTest(TestCase): def testToSignalsDupl(self): try: Cosimulation(exe + ".cosimToSignalsDupl", **allSigs) - except CosimulationError, e: + except CosimulationError as e: self.assertEqual(e.kind, _error.DuplicateSigNames) else: self.fail() diff --git a/myhdl/test/core/test_Signal.py b/myhdl/test/core/test_Signal.py index 80ef3c1d..4e3a6bbd 100644 --- a/myhdl/test/core/test_Signal.py +++ b/myhdl/test/core/test_Signal.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for Signal """ +from __future__ import absolute_import import operator @@ -114,16 +115,16 @@ class SigTest(TestCase): cur = copy.copy(s.val) s.next = n # assigning to next should not change current value ... - self.assert_(s.val == cur) + self.assertTrue(s.val == cur) s._update() - self.assert_(s.val == n) + self.assertTrue(s.val == n) def testNextType(self): """ sig.next = n should fail on access if type(n) incompatible """ i = 0 for s in (self.sigs + self.incompatibleSigs): for n in (self.vals + self.incompatibleVals): - self.assert_(isinstance(s.val, s._type)) + self.assertTrue(isinstance(s.val, s._type)) if isinstance(s.val, (int, long, intbv)): t = (int, long, intbv) else: @@ -137,7 +138,7 @@ class SigTest(TestCase): pass else: self.fail() - self.assert_(i >= len(self.incompatibleSigs), "Nothing tested %s" %i) + self.assertTrue(i >= len(self.incompatibleSigs), "Nothing tested %s" %i) def testAfterUpdate(self): """ updated val and next should be equal but not identical """ @@ -162,7 +163,7 @@ class SigTest(TestCase): s.next[3] = 5 else: s.next # plain read access - self.assert_(s.val is not s.next, `s.val`) + self.assertTrue(s.val is not s.next, `s.val`) def testUpdatePosedge(self): """ update on posedge should return event and posedge waiters """ @@ -521,7 +522,7 @@ class TestSignalIntBvIndexing(TestCase): res = sbv[i:j] resi = sbvi[i:j] except ValueError: - self.assert_(i<=j) + self.assertTrue(i<=j) continue ref = long(getSlice(s, i, j), 2) self.assertEqual(res, ref) diff --git a/myhdl/test/core/test_Simulation.py b/myhdl/test/core/test_Simulation.py index d01b12ff..545d184f 100644 --- a/myhdl/test/core/test_Simulation.py +++ b/myhdl/test/core/test_Simulation.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run unit tests for Simulation """ +from __future__ import absolute_import import unittest @@ -42,7 +43,7 @@ class SimArgs(TestCase): def test1(self): try: Simulation(None) - except SimulationError, e: + except SimulationError as e: self.assertEqual(e.kind, _error.ArgType) except: self.fail() @@ -53,7 +54,7 @@ class SimArgs(TestCase): i = g() try: Simulation(i, i) - except SimulationError, e: + except SimulationError as e: self.assertEqual(e.kind, _error.DuplicatedArg) except: self.fail() @@ -254,7 +255,7 @@ class JoinedGen(TestCase): self.assertEqual(sig2.val, 1) self.assertEqual(now(), offset + td * max(n0, n1, n2)) - raise StopSimulation, "Joined concurrent generator yield" + raise StopSimulation("Joined concurrent generator yield") def testYieldJoinedGen(self): Simulation(self.bench()).run(quiet=QUIET) @@ -286,7 +287,7 @@ class SignalUpdateFirst(TestCase): self.assertEqual(Q.val, 1) # control self.assertEqual(R.val, 1) # control self.assertEqual(S.val, 1) # control - raise StopSimulation, "Signal update test" + raise StopSimulation("Signal update test") return process() @@ -324,7 +325,7 @@ class YieldZeroDelay(TestCase): yield sig2.posedge self.assertEqual(now(), offset + n2*td) - raise StopSimulation, "Zero delay yield" + raise StopSimulation("Zero delay yield") def testYieldZeroDelay(self): Simulation(self.bench()).run(quiet=QUIET) @@ -360,7 +361,7 @@ class YieldConcurrentGen(TestCase): yield sig2.posedge self.assertEqual(now(), offset + n2*td) - raise StopSimulation, "Concurrent generator yield" + raise StopSimulation("Concurrent generator yield") def testYieldConcurrentGen(self): Simulation(self.bench()).run(quiet=QUIET) @@ -410,7 +411,7 @@ class YieldGen(TestCase): for nlist in nlists: yield task(nlist) self.assertEqual(shared.cnt, expected[-1]) - raise StopSimulation, "Generator yield" + raise StopSimulation("Generator yield") return(module(), clkGen()) @@ -469,7 +470,7 @@ class DeltaCycleOrder(TestCase): yield clk.posedge yield clk.posedge self.assertEqual(z.val, function(v[0], v[1], v[2], v[3])) - raise StopSimulation, "Delta cycle order" + raise StopSimulation("Delta cycle order") inputGen = [inGen(i) for i in range(4)] instance = [clkGen(), deltaGen(), logic(), stimulus(), inputGen] @@ -692,7 +693,7 @@ class Waveform(TestCase): self.sig.delay = sigdelay def response(self, clause, expected): - self.assert_(len(expected) > 100) # we should test something + self.assertTrue(len(expected) > 100) # we should test something i = 0 while 1: yield clause @@ -712,7 +713,7 @@ class Waveform(TestCase): expected = getExpectedTimes(self.waveform, isPosedge) response = self.response(clause=s.posedge, expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) def testNegedge(self): """ Negedge waveform test """ @@ -721,7 +722,7 @@ class Waveform(TestCase): expected = getExpectedTimes(self.waveform, isNegedge) response = self.response(clause=s.negedge, expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) def testEdge(self): """ Edge waveform test """ @@ -731,7 +732,7 @@ class Waveform(TestCase): response = self.response(clause=(s.negedge, s.posedge), expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) def testEvent(self): """ Event waveform test """ @@ -741,7 +742,7 @@ class Waveform(TestCase): # print expected response = self.response(clause=s, expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) def testRedundantEvents(self): """ Redundant event waveform test """ @@ -750,7 +751,7 @@ class Waveform(TestCase): expected = getExpectedTimes(self.waveform, isEvent) response = self.response(clause=(s,) * 6, expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) def testRedundantEventAndEdges(self): """ Redundant edge waveform test """ @@ -760,7 +761,7 @@ class Waveform(TestCase): response = self.response(clause=(s, s.negedge, s.posedge), expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) def testRedundantPosedges(self): """ Redundant posedge waveform test """ @@ -769,7 +770,7 @@ class Waveform(TestCase): expected = getExpectedTimes(self.waveform, isPosedge) response = self.response(clause=(s.posedge,) * 3, expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) def testRedundantNegedges(self): """ Redundant negedge waveform test """ @@ -778,7 +779,7 @@ class Waveform(TestCase): expected = getExpectedTimes(self.waveform, isNegedge) response = self.response(clause=(s.negedge,) * 9, expected=expected) self.runSim(Simulation(stimulus, response)) - self.assert_(self.duration <= now()) + self.assertTrue(self.duration <= now()) class WaveformSigDelay(Waveform): diff --git a/myhdl/test/core/test_all.py b/myhdl/test/core/test_all.py index ea4253b9..6eca864c 100644 --- a/myhdl/test/core/test_all.py +++ b/myhdl/test/core/test_all.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run all myhdl unit tests. """ +from __future__ import absolute_import import test_Simulation, test_Signal, test_intbv, test_Cosimulation, test_misc, \ diff --git a/myhdl/test/core/test_always.py b/myhdl/test/core/test_always.py index 415e1352..0269aae2 100644 --- a/myhdl/test/core/test_always.py +++ b/myhdl/test/core/test_always.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for the @always decorator """ +from __future__ import absolute_import import random @@ -52,7 +53,7 @@ class AlwaysCompilationTest(TestCase): h = 5 try: always(delay(3))(h) - except AlwaysError, e: + except AlwaysError as e: self.assertEqual(e.kind, _error.ArgType) else: self.fail() @@ -62,7 +63,7 @@ class AlwaysCompilationTest(TestCase): @always(delay(3)) def h(): yield None - except AlwaysError, e: + except AlwaysError as e: self.assertEqual(e.kind, _error.ArgType) else: self.fail() @@ -72,7 +73,7 @@ class AlwaysCompilationTest(TestCase): @always(delay(3)) def h(n): return n - except AlwaysError, e: + except AlwaysError as e: self.assertEqual(e.kind, _error.NrOfArgs) else: self.fail() @@ -82,7 +83,7 @@ class AlwaysCompilationTest(TestCase): @always def h(n): return n - except AlwaysError, e: + except AlwaysError as e: self.assertEqual(e.kind, _error.DecArgType) else: self.fail() @@ -92,7 +93,7 @@ class AlwaysCompilationTest(TestCase): @always(g) def h(n): return n - except AlwaysError, e: + except AlwaysError as e: self.assertEqual(e.kind, _error.DecArgType) else: self.fail() diff --git a/myhdl/test/core/test_always_comb.py b/myhdl/test/core/test_always_comb.py index 2581f9da..85e0d150 100644 --- a/myhdl/test/core/test_always_comb.py +++ b/myhdl/test/core/test_always_comb.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for always_comb """ +from __future__ import absolute_import import random @@ -50,7 +51,7 @@ class AlwaysCombCompilationTest(TestCase): h = 5 try: always_comb(h) - except AlwaysCombError, e: + except AlwaysCombError as e: self.assertEqual(e.kind, _error.ArgType) else: self.fail() @@ -60,7 +61,7 @@ class AlwaysCombCompilationTest(TestCase): yield None try: always_comb(h) - except AlwaysCombError, e: + except AlwaysCombError as e: self.assertEqual(e.kind, _error.ArgType) else: self.fail() @@ -70,7 +71,7 @@ class AlwaysCombCompilationTest(TestCase): return n try: always_comb(h) - except AlwaysCombError, e: + except AlwaysCombError as e: self.assertEqual(e.kind, _error.NrOfArgs) else: self.fail() @@ -135,7 +136,7 @@ class AlwaysCombCompilationTest(TestCase): a += 1 try: g = always_comb(h).gen - except AlwaysCombError, e: + except AlwaysCombError as e: self.assertEqual(e.kind, _error.SignalAsInout % "c") else: self.fail() @@ -147,7 +148,7 @@ class AlwaysCombCompilationTest(TestCase): x.next = c try: g = always_comb(h).gen - except AlwaysCombError, e: + except AlwaysCombError as e: self.assertEqual(e.kind, _error.SignalAsInout % "c") else: self.fail() @@ -203,7 +204,7 @@ class AlwaysCombCompilationTest(TestCase): g = a try: g = always_comb(h) - except AlwaysCombError, e: + except AlwaysCombError as e: self.assertEqual(e.kind, _error.EmbeddedFunction) else: self.fail() @@ -249,7 +250,7 @@ class AlwaysCombSimulationTest1(TestCase): yield clk.posedge yield clk.negedge self.assertEqual(x, z) - raise StopSimulation, "always_comb simulation test" + raise StopSimulation("always_comb simulation test") return instances() @@ -346,7 +347,7 @@ class AlwaysCombSimulationTest2(TestCase): yield clk.posedge yield clk.negedge self.assertEqual(x, z) - raise StopSimulation, "always_comb simulation test" + raise StopSimulation("always_comb simulation test") return comb, gen, clkGen(), stimulus() diff --git a/myhdl/test/core/test_bin.py b/myhdl/test/core/test_bin.py index b9860424..34df37a3 100644 --- a/myhdl/test/core/test_bin.py +++ b/myhdl/test/core/test_bin.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for bin """ +from __future__ import absolute_import import random diff --git a/myhdl/test/core/test_concat.py b/myhdl/test/core/test_concat.py index 2bc56d73..812eb7d0 100644 --- a/myhdl/test/core/test_concat.py +++ b/myhdl/test/core/test_concat.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the concatunit tests. """ +from __future__ import absolute_import import unittest diff --git a/myhdl/test/core/test_enum.py b/myhdl/test/core/test_enum.py index 3a7f4c46..f0b78e48 100644 --- a/myhdl/test/core/test_enum.py +++ b/myhdl/test/core/test_enum.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for enum """ +from __future__ import absolute_import import random @@ -72,15 +73,15 @@ class TestEnum(TestCase): self.fail() def testHomograph(self): - self.assert_(t_State is not t_Homograph) + self.assertTrue(t_State is not t_Homograph) def testHomographLiteral(self): - self.assert_(t_State.SEARCH is not t_Homograph.SEARCH) + self.assertTrue(t_State.SEARCH is not t_Homograph.SEARCH) def testItemCopy(self): e = copy.deepcopy(t_State.SEARCH) - self.assert_(e == t_State.SEARCH) - self.assert_(e != t_State.CONFIRM) + self.assertTrue(e == t_State.SEARCH) + self.assertTrue(e != t_State.CONFIRM) if __name__ == "__main__": diff --git a/myhdl/test/core/test_inferWaiter.py b/myhdl/test/core/test_inferWaiter.py index 63aa6fce..df0d19b2 100644 --- a/myhdl/test/core/test_inferWaiter.py +++ b/myhdl/test/core/test_inferWaiter.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for inferWaiter """ +from __future__ import absolute_import import random from random import randrange diff --git a/myhdl/test/core/test_instance.py b/myhdl/test/core/test_instance.py index 4f2b4d32..ea977f66 100644 --- a/myhdl/test/core/test_instance.py +++ b/myhdl/test/core/test_instance.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for instance """ +from __future__ import absolute_import import random @@ -49,7 +50,7 @@ class InstanceCompilationTest(TestCase): h = 5 try: instance(h) - except InstanceError, e: + except InstanceError as e: self.assertEqual(e.kind, _error.ArgType) else: self.fail() @@ -59,7 +60,7 @@ class InstanceCompilationTest(TestCase): @instance def h(): return None - except InstanceError, e: + except InstanceError as e: self.assertEqual(e.kind, _error.ArgType) else: self.fail() @@ -69,7 +70,7 @@ class InstanceCompilationTest(TestCase): @instance def h(n): yield n - except InstanceError, e: + except InstanceError as e: self.assertEqual(e.kind, _error.NrOfArgs) else: self.fail() diff --git a/myhdl/test/core/test_intbv.py b/myhdl/test/core/test_intbv.py index 2a82272a..091e2d95 100644 --- a/myhdl/test/core/test_intbv.py +++ b/myhdl/test/core/test_intbv.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the intbv unit tests. """ +from __future__ import absolute_import import unittest @@ -121,7 +122,7 @@ class TestIntBvIndexing(TestCase): res = bv[i:j] resi = bvi[i:j] except ValueError: - self.assert_(i<=j) + self.assertTrue(i<=j) continue ref = long(getSlice(s, i, j), 2) self.assertEqual(res, ref) @@ -189,7 +190,7 @@ class TestIntBvIndexing(TestCase): try: bv[i:j] = val except ValueError: - self.assert_(i<=j or val >= 2**(i-j)) + self.assertTrue(i<=j or val >= 2**(i-j)) continue else: ref = long(setSlice(s, i, j, extv), 2) @@ -199,7 +200,7 @@ class TestIntBvIndexing(TestCase): try: bvi[i:j] = vali except ValueError: - self.assert_(vali >= 2**(i-j)) + self.assertTrue(vali >= 2**(i-j)) continue else: refi = ~long(setSlice(s, i, j, extv), 2) @@ -295,8 +296,8 @@ class TestIntBvAsInt(TestCase): self.assertEqual(r1, ref) self.assertEqual(r2, ref) self.assertEqual(r3, ref) - self.assert_(r1 is bi1) - self.assert_(r3 is bi3) + self.assertTrue(r1 is bi1) + self.assertTrue(r3 is bi3) def unaryCheck(self, op, imin=0, imax=None): self.seqSetup(imin=imin, imax=imax) diff --git a/myhdl/test/core/test_misc.py b/myhdl/test/core/test_misc.py index c6c38d21..6a0c541d 100644 --- a/myhdl/test/core/test_misc.py +++ b/myhdl/test/core/test_misc.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for Signal """ +from __future__ import absolute_import import random @@ -71,7 +72,7 @@ class InstancesTest(TestCase): # that would become part of the instances also! self.assertEqual(len(i), 4) for e in (D_1, A_1, B_1, C_1): - self.assert_(e in i) + self.assertTrue(e in i) if __name__ == "__main__": diff --git a/myhdl/test/core/test_modbv.py b/myhdl/test/core/test_modbv.py index 46d2d555..1b3d2d14 100644 --- a/myhdl/test/core/test_modbv.py +++ b/myhdl/test/core/test_modbv.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the modbv unit tests. """ +from __future__ import absolute_import import unittest diff --git a/myhdl/test/core/test_signed.py b/myhdl/test/core/test_signed.py index bd4a5aa1..7e496b8b 100644 --- a/myhdl/test/core/test_signed.py +++ b/myhdl/test/core/test_signed.py @@ -19,6 +19,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the intbv.signed() unit tests. """ +from __future__ import absolute_import import unittest from unittest import TestCase diff --git a/myhdl/test/core/test_traceSignals.py b/myhdl/test/core/test_traceSignals.py index 81ff9a26..b8fde40f 100644 --- a/myhdl/test/core/test_traceSignals.py +++ b/myhdl/test/core/test_traceSignals.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for traceSignals """ +from __future__ import absolute_import import random @@ -103,7 +104,7 @@ class TestTraceSigs(TestCase): def testMultipleTraces(self): try: dut = top3() - except TraceSignalsError, e: + except TraceSignalsError as e: self.assertEqual(e.kind, _error.MultipleTraces) else: self.fail() @@ -111,7 +112,7 @@ class TestTraceSigs(TestCase): def testArgType1(self): try: dut = traceSignals([1, 2]) - except TraceSignalsError, e: + except TraceSignalsError as e: self.assertEqual(e.kind, _error.ArgType) else: self.fail() @@ -121,39 +122,39 @@ class TestTraceSigs(TestCase): from myhdl._extractHierarchy import _error try: dut = traceSignals(dummy) - except ExtractHierarchyError, e: + except ExtractHierarchyError as e: self.assertEqual(e.kind, _error.InconsistentToplevel % (2, "dummy")) else: self.fail() def testHierarchicalTrace1(self): - p = "%s.vcd" % fun.func_name + p = "%s.vcd" % fun.__name__ top() - self.assert_(path.exists(p)) + self.assertTrue(path.exists(p)) def testHierarchicalTrace2(self): - pdut = "%s.vcd" % top.func_name - psub = "%s.vcd" % fun.func_name + pdut = "%s.vcd" % top.__name__ + psub = "%s.vcd" % fun.__name__ dut = traceSignals(top) - self.assert_(path.exists(pdut)) - self.assert_(not path.exists(psub)) + self.assertTrue(path.exists(pdut)) + self.assertTrue(not path.exists(psub)) def testBackupOutputFile(self): - p = "%s.vcd" % fun.func_name + p = "%s.vcd" % fun.__name__ dut = traceSignals(fun) Simulation(dut).run(1000, quiet=QUIET) _simulator._tf.close() _simulator._tracing = 0 size = path.getsize(p) pbak = p + '.' + str(path.getmtime(p)) - self.assert_(not path.exists(pbak)) + self.assertTrue(not path.exists(pbak)) dut = traceSignals(fun) _simulator._tf.close() _simulator._tracing = 0 - self.assert_(path.exists(p)) - self.assert_(path.exists(pbak)) - self.assert_(path.getsize(pbak) == size) - self.assert_(path.getsize(p) < size) + self.assertTrue(path.exists(p)) + self.assertTrue(path.exists(pbak)) + self.assertTrue(path.getsize(pbak) == size) + self.assertTrue(path.getsize(p) < size) diff --git a/myhdl/test/core/test_unparse.py b/myhdl/test/core/test_unparse.py index 3cd358f0..f4acf72a 100644 --- a/myhdl/test/core/test_unparse.py +++ b/myhdl/test/core/test_unparse.py @@ -18,6 +18,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA """ Run the unit tests for _unparse """ +from __future__ import absolute_import import unittest diff --git a/myhdl/test/core2/test_ShadowSignal.py b/myhdl/test/core2/test_ShadowSignal.py index e4e1b9de..62f65a05 100644 --- a/myhdl/test/core2/test_ShadowSignal.py +++ b/myhdl/test/core2/test_ShadowSignal.py @@ -1,3 +1,4 @@ +from __future__ import absolute_import from myhdl import * def bench_SliceSignal(): diff --git a/setup.py b/setup.py index 79f18e35..04734079 100644 --- a/setup.py +++ b/setup.py @@ -1,5 +1,6 @@ """ myhdl's distutils distribution and installation script. """ +from __future__ import print_function import sys requiredVersion = (2, 6) @@ -12,11 +13,11 @@ versionError = "ERROR: myhdl requires Python %s or higher" % requiredVersionStr try: sys.version_info except: - print versionError + print(versionError) raise SystemExit(1) if sys.version_info < requiredVersion: - print versionError + print(versionError) raise SystemExit(1) from distutils.core import setup