Merge branch 'jck-refactoring'

.travis.yml

@@ -3,6 +3,7 @@ python:
   - "2.6"
   - "2.7"
   - "pypy"
+  - "3.4"
 
 before_install:
   - if [ $CI_TARGET == "icarus" ]; then
@@ -22,6 +23,10 @@ env:
   - CI_TARGET=icarus
   - CI_TARGET=ghdl
 
+matrix:
+  allow_failures:
+    - python: "3.4"
+
 script: ./ci.sh
 
 notifications:

myhdl/_Cosimulation.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the Cosimulation class """
+from __future__ import absolute_import
 
 
 import sys
@@ -77,7 +78,7 @@ class Cosimulation(object):
             arglist[0] = os.path.basename(p)
             try:
                 os.execvp(p, arglist)
-            except OSError, e:
+            except OSError as e:
                 raise CosimulationError(_error.OSError, str(e))
         else:
             os.close(wt)

myhdl/_ShadowSignal.py

@@ -21,6 +21,7 @@
 
 
 """
+from __future__ import absolute_import
 
 import warnings
 from copy import deepcopy

myhdl/_Signal.py

@@ -26,6 +26,8 @@ posedge -- callable to model a rising edge on a signal in a yield statement
 negedge -- callable to model a falling edge on a signal in a yield statement
 
 """
+from __future__ import absolute_import
+from __future__ import print_function
 
 from inspect import currentframe, getouterframes
 from copy import copy, deepcopy
@@ -295,16 +297,16 @@ class _Signal(object):
 
     # vcd print methods
     def _printVcdStr(self):
-        print >> sim._tf, "s%s %s" % (str(self._val), self._code)
+        print("s%s %s" % (str(self._val), self._code), file=sim._tf)
         
     def _printVcdHex(self):
-        print >> sim._tf, "s%s %s" % (hex(self._val), self._code)
+        print("s%s %s" % (hex(self._val), self._code), file=sim._tf)
 
     def _printVcdBit(self):
-        print >> sim._tf, "%d%s" % (self._val, self._code)
+        print("%d%s" % (self._val, self._code), file=sim._tf)
 
     def _printVcdVec(self):
-        print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
+        print("b%s %s" % (bin(self._val, self._nrbits), self._code), file=sim._tf)
 
     ### use call interface for shadow signals ###
     def __call__(self, left, right=None):
@@ -510,14 +512,14 @@ class _Signal(object):
 
     # augmented assignment not supported
     def _augm(self):
-        raise TypeError, "Signal object doesn't support augmented assignment"
+        raise TypeError("Signal object doesn't support augmented assignment")
 
     __iadd__ = __isub__ = __idiv__ = __imul__ = __ipow__ = __imod__ = _augm
     __ior__ = __iand__ = __ixor__ = __irshift__ = __ilshift__ = _augm
 
     # index and slice assignment not supported
     def __setitem__(self, key, val):
-        raise TypeError, "Signal object doesn't support item/slice assignment"
+        raise TypeError("Signal object doesn't support item/slice assignment")
 
 
     # continues assignment support

myhdl/_Simulation.py

@@ -18,6 +18,8 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the Simulation class """
+from __future__ import absolute_import
+from __future__ import print_function
 
 
 import sys
@@ -158,7 +160,7 @@ class Simulation(object):
                     _futureEvents.sort()
                     t = _simulator._time = _futureEvents[0][0]
                     if tracing:
-                        print >> tracefile, "#%s" % t
+                        print("#%s" % t, file=tracefile)
                     if cosim:
                         cosim._put(t)
                     while _futureEvents:
@@ -188,7 +190,7 @@ class Simulation(object):
                 self._finished = True
                 return 0
 
-            except Exception, e:
+            except Exception as e:
                 if tracing:
                     tracefile.flush()
                 # if the exception came from a yield, make sure we can resume

myhdl/_Waiter.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the _Waiter class """
+from __future__ import absolute_import
 
 
 from types import GeneratorType

myhdl/__init__.py

@@ -49,6 +49,8 @@ traceSignals -- function that enables signal tracing in a VCD file
 toVerilog -- function that converts a design to Verilog
 
 """
+from __future__ import absolute_import
+from __future__ import print_function
 
 __version__ = "0.9dev"
 
@@ -106,36 +108,36 @@ class ToVHDLWarning(ConversionWarning):
 # warnings.filterwarnings('always', r".*", ToVerilogWarning)
 
 def showwarning(message, category, filename, lineno, *args):
-    print >> sys.stderr, "** %s: %s" % (category.__name__, message)
+    print("** %s: %s" % (category.__name__, message), file=sys.stderr)
 
 warnings.showwarning = showwarning
 
 
-from _bin import bin
+from ._bin import bin
-from _concat import concat
+from ._concat import concat
-from _intbv import intbv
+from ._intbv import intbv
-from _modbv import modbv
+from ._modbv import modbv
-from _join import join
+from ._join import join
-from _Signal import posedge, negedge, Signal, SignalType
+from ._Signal import posedge, negedge, Signal, SignalType
-from _ShadowSignal import ConcatSignal
+from ._ShadowSignal import ConcatSignal
-from _ShadowSignal import TristateSignal
+from ._ShadowSignal import TristateSignal
-from _simulator import now
+from ._simulator import now
-from _delay import delay
+from ._delay import delay
-from _Cosimulation import Cosimulation
+from ._Cosimulation import Cosimulation
-from _Simulation import Simulation
+from ._Simulation import Simulation
-from _misc import instances, downrange
+from ._misc import instances, downrange
-from _always_comb import always_comb
+from ._always_comb import always_comb
-from _always_seq import always_seq, ResetSignal
+from ._always_seq import always_seq, ResetSignal
-from _always import always
+from ._always import always
-from _instance import instance
+from ._instance import instance
-from _enum import enum, EnumType, EnumItemType
+from ._enum import enum, EnumType, EnumItemType
-from _traceSignals import traceSignals
+from ._traceSignals import traceSignals
 
 from myhdl import conversion
-from conversion import toVerilog
+from .conversion import toVerilog
-from conversion import toVHDL
+from .conversion import toVHDL
 
-from _tristate import Tristate
+from ._tristate import Tristate
 
 
 __all__ = ["bin",

myhdl/_always.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always function. """
+from __future__ import absolute_import
 
 
 from types import FunctionType
@@ -53,7 +54,7 @@ def always(*args):
             raise AlwaysError(_error.ArgType)
         if _isGenFunc(func):
             raise AlwaysError(_error.ArgType)
-        if func.func_code.co_argcount > 0:
+        if func.__code__.co_argcount > 0:
             raise AlwaysError(_error.NrOfArgs)
         return _Always(func, args)
     return _always_decorator

myhdl/_always_comb.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always_comb function. """
+from __future__ import absolute_import
 
 import sys
 import inspect
@@ -47,16 +48,16 @@ def always_comb(func):
         raise AlwaysCombError(_error.ArgType)
     if _isGenFunc(func):
         raise AlwaysCombError(_error.ArgType)
-    if func.func_code.co_argcount > 0:
+    if func.__code__.co_argcount > 0:
         raise AlwaysCombError(_error.NrOfArgs)
-    varnames = func.func_code.co_varnames
+    varnames = func.__code__.co_varnames
     symdict = {}
-    for n, v in func.func_globals.items():
+    for n, v in func.__globals__.items():
         if n not in varnames:
             symdict[n] = v
     # handle free variables
-    if func.func_code.co_freevars:
+    if func.__code__.co_freevars:
-        for n, c in zip(func.func_code.co_freevars, func.func_closure):
+        for n, c in zip(func.__code__.co_freevars, func.__closure__):
             try:
                 obj = _cell_deref(c)
                 symdict[n] = obj

myhdl/_always_seq.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always_seq decorator. """
+from __future__ import absolute_import
 
 
 import sys
@@ -75,7 +76,7 @@ def always_seq(edge, reset):
             raise AlwaysSeqError(_error.ArgType)
         if _isGenFunc(func):
             raise AlwaysSeqError(_error.ArgType)
-        if func.func_code.co_argcount > 0:
+        if func.__code__.co_argcount > 0:
             raise AlwaysSeqError(_error.NrOfArgs)
         return _AlwaysSeq(func, edge, reset)
     return _always_seq_decorator
@@ -106,14 +107,14 @@ class _AlwaysSeq(_Instantiator):
 
         # find symdict
         # similar to always_comb, but in class constructor
-        varnames = func.func_code.co_varnames
+        varnames = func.__code__.co_varnames
         symdict = {}
-        for n, v in func.func_globals.items():
+        for n, v in func.__globals__.items():
             if n not in varnames:
                 symdict[n] = v
         # handle free variables
-        if func.func_code.co_freevars:
+        if func.__code__.co_freevars:
-            for n, c in zip(func.func_code.co_freevars, func.func_closure):
+            for n, c in zip(func.__code__.co_freevars, func.__closure__):
                 try:
                     obj = _cell_deref(c)
                     symdict[n] = obj

myhdl/_cell_deref.py

@@ -1,6 +1,7 @@
+
 # cell dereferencing hack, thanks to Samuele Pedroni
 
-import new
+from types import FunctionType
 
 def _proto_acc(v=None):
     def acc():
@@ -9,10 +10,10 @@ def _proto_acc(v=None):
 
 _acc0 = _proto_acc()
 
-_make_acc = lambda cell: (new.function (_acc0.func_code,
+_make_acc = lambda cell: (FunctionType(_acc0.__code__,
-                                        _acc0.func_globals,
+                                        _acc0.__globals__,
                                         '#cell_acc',
-                                        _acc0.func_defaults,
+                                        _acc0.__defaults__,
                                         (cell,)
                                         )
                           )

myhdl/_concat.py

@@ -20,6 +20,7 @@
 """ module with the concat function.
 
 """
+from __future__ import absolute_import
 
 from myhdl._intbv import intbv
 from myhdl._Signal import _Signal
@@ -69,7 +70,7 @@ def concat(base, *args):
             raise TypeError("concat: inappropriate argument type: %s" \
                             % type(arg))
         if not w:
-            raise TypeError, "concat: arg on pos %d should have length" % (i+1)
+            raise TypeError("concat: arg on pos %d should have length" % (i+1))
         width += w
         val = val << w | v & (1L << w)-1
  

myhdl/_delay.py

@@ -34,5 +34,5 @@ class delay(object):
 
         """
         if not isinstance(val, (int, long)) or val < 0:
-            raise TypeError, _errmsg
+            raise TypeError(_errmsg)
         self._time = val

myhdl/_enum.py

@@ -20,6 +20,7 @@
 """ Module that implements enum.
 
 """
+from __future__ import absolute_import
 
 
 from types import StringType

myhdl/_extractHierarchy.py

@@ -20,6 +20,7 @@
 """ myhdl _extractHierarchy module.
 
 """
+from __future__ import absolute_import
 
 
 import sys
@@ -320,10 +321,10 @@ class _HierExtr(object):
                     #All nested functions will be in co_consts
                     if func:
                         local_gens = []
-                        consts = func.func_code.co_consts
+                        consts = func.__code__.co_consts
                         for item in _flatten(arg):
                             genfunc = _genfunc(item)
-                            if genfunc.func_code in consts:
+                            if genfunc.__code__ in consts:
                                 local_gens.append(item)
                         if local_gens:
                             objlist = _resolveRefs(symdict, local_gens)

myhdl/_instance.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always function. """
+from __future__ import absolute_import
 
 
 from types import FunctionType
@@ -37,7 +38,7 @@ def instance(genFunc):
         raise InstanceError(_error.ArgType)
     if not _isGenFunc(genFunc):
         raise InstanceError(_error.ArgType)
-    if genFunc.func_code.co_argcount > 0:
+    if genFunc.__code__.co_argcount > 0:
         raise InstanceError(_error.NrOfArgs)
     return _Instantiator(genFunc)
 

myhdl/_intbv.py

@@ -18,6 +18,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the intbv class """
+from __future__ import absolute_import
 
 
 
@@ -113,7 +114,7 @@ class intbv(object):
     # iterator method
     def __iter__(self):
         if not self._nrbits:
-            raise TypeError, "Cannot iterate over unsized intbv"
+            raise TypeError("Cannot iterate over unsized intbv")
         return iter([self[i] for i in range(self._nrbits-1, -1, -1)])
 
     # logical testing
@@ -136,14 +137,14 @@ class intbv(object):
                 j = 0
             j = int(j)
             if j < 0:
-                raise ValueError, "intbv[i:j] requires j >= 0\n" \
+                raise ValueError("intbv[i:j] requires j >= 0\n" \
-                      "            j == %s" % j
+                      "            j == %s" % j)
             if i is None: # default
                 return intbv(self._val >> j)
             i = int(i)
             if i <= j:
-                raise ValueError, "intbv[i:j] requires i > j\n" \
+                raise ValueError("intbv[i:j] requires i > j\n" \
-                      "            i, j == %s, %s" % (i, j)
+                      "            i, j == %s, %s" % (i, j))
             res = intbv((self._val & (1L << i)-1) >> j, _nrbits=i-j)
             return res
         else:
@@ -162,8 +163,8 @@ class intbv(object):
                 j = 0
             j = int(j)
             if j < 0:
-                raise ValueError, "intbv[i:j] = v requires j >= 0\n" \
+                raise ValueError("intbv[i:j] = v requires j >= 0\n" \
-                      "            j == %s" % j
+                      "            j == %s" % j)
             if i is None: # default
                 q = self._val % (1L << j)
                 self._val = val * (1L << j) + q
@@ -171,12 +172,12 @@ class intbv(object):
                 return
             i = int(i)
             if i <= j:
-                raise ValueError, "intbv[i:j] = v requires i > j\n" \
+                raise ValueError("intbv[i:j] = v requires i > j\n" \
-                      "            i, j, v == %s, %s, %s" % (i, j, val)
+                      "            i, j, v == %s, %s, %s" % (i, j, val))
             lim = (1L << (i-j))
             if val >= lim or val < -lim:
-                raise ValueError, "intbv[i:j] = v abs(v) too large\n" \
+                raise ValueError("intbv[i:j] = v abs(v) too large\n" \
-                      "            i, j, v == %s, %s, %s" % (i, j, val)
+                      "            i, j, v == %s, %s, %s" % (i, j, val))
             mask = (lim-1) << j
             self._val &= ~mask
             self._val |= (val << j)
@@ -188,8 +189,8 @@ class intbv(object):
             elif val == 0:
                 self._val &= ~(1L << i)
             else:
-                raise ValueError, "intbv[i] = v requires v in (0, 1)\n" \
+                raise ValueError("intbv[i] = v requires v in (0, 1)\n" \
-                      "            i == %s " % i
+                      "            i == %s " % i)
                
             self._handleBounds()
 

myhdl/_misc.py

@@ -24,21 +24,19 @@ instances -- function that returns instances in a generator function
 downrange -- function that returns a downward range
 
 """
+from __future__ import absolute_import
 
 
 import sys
 import inspect
 
-from types import GeneratorType
-from types import GeneratorType, ListType, TupleType
-
 from myhdl._Cosimulation import Cosimulation
 from myhdl._instance import _Instantiator
       
 def _isGenSeq(obj):
     if isinstance(obj, (Cosimulation, _Instantiator)):
         return True
-    if not isinstance(obj, (ListType, TupleType, set)):
+    if not isinstance(obj, (list, tuple, set)):
         return False
 ##     if not obj:
 ##         return False

myhdl/_modbv.py

@@ -18,8 +18,9 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the modbv class """
+from __future__ import absolute_import
 
-from _intbv import intbv
+from ._intbv import intbv
 
 class modbv(intbv):
     __slots__ = []
@@ -44,14 +45,14 @@ class modbv(intbv):
                 j = 0
             j = int(j)
             if j < 0:
-                raise ValueError, "modbv[i:j] requires j >= 0\n" \
+                raise ValueError("modbv[i:j] requires j >= 0\n" \
-                      "            j == %s" % j
+                      "            j == %s" % j)
             if i is None: # default
                 return modbv(self._val >> j)
             i = int(i)
             if i <= j:
-                raise ValueError, "modbv[i:j] requires i > j\n" \
+                raise ValueError("modbv[i:j] requires i > j\n" \
-                      "            i, j == %s, %s" % (i, j)
+                      "            i, j == %s, %s" % (i, j))
             res = modbv((self._val & (1L << i)-1) >> j, _nrbits=i-j)
             return res
         else:

myhdl/_resolverefs.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import ast
 from types import FunctionType
 

myhdl/_traceSignals.py

@@ -20,6 +20,8 @@
 """ myhdl traceSignals module.
 
 """
+from __future__ import absolute_import
+from __future__ import print_function
 
 
 
@@ -74,7 +76,7 @@ class _TraceSignalsClass(object):
         _tracing = 1
         try:
             if self.name is None:
-                name = dut.func_name
+                name = dut.__name__
             else:
                 name = str(self.name)
             if name is None:
@@ -118,16 +120,16 @@ def _namecode(n):
     return code
 
 def _writeVcdHeader(f, timescale):
-    print >> f, "$date"
+    print("$date", file=f)
-    print >> f, "    %s" % time.asctime()
+    print("    %s" % time.asctime(), file=f)
-    print >> f, "$end"
+    print("$end", file=f)
-    print >> f, "$version"
+    print("$version", file=f)
-    print >> f, "    MyHDL %s" % __version__
+    print("    MyHDL %s" % __version__, file=f)
-    print >> f, "$end"
+    print("$end", file=f)
-    print >> f, "$timescale"
+    print("$timescale", file=f)
-    print >> f, "    %s" % timescale
+    print("    %s" % timescale, file=f)
-    print >> f, "$end"
+    print("$end", file=f)
-    print >> f
+    print(file=f)
 
 def _writeVcdSigs(f, hierarchy, tracelists):
     curlevel = 0
@@ -143,8 +145,8 @@ def _writeVcdSigs(f, hierarchy, tracelists):
         assert(delta >= -1)
         if delta >= 0:
             for i in range(delta + 1):
-                print >> f, "$upscope $end"
+                print("$upscope $end", file=f)
-        print >> f, "$scope module %s $end" % name
+        print("$scope module %s $end" % name, file=f)
         for n, s in sigdict.items():
             if s._val is None:
                 raise ValueError("%s of module %s has no initial value" % (n, name))
@@ -156,11 +158,11 @@ def _writeVcdSigs(f, hierarchy, tracelists):
             # use real for enum strings
             if w and not isinstance(s._val, EnumItemType):
                 if w == 1:
-                    print >> f, "$var reg 1 %s %s $end" % (s._code, n)
+                    print("$var reg 1 %s %s $end" % (s._code, n), file=f)
                 else:
-                    print >> f, "$var reg %s %s %s $end" % (w, s._code, n)
+                    print("$var reg %s %s %s $end" % (w, s._code, n), file=f)
             else:
-                print >> f, "$var real 1 %s %s $end" % (s._code, n)
+                print("$var real 1 %s %s $end" % (s._code, n), file=f)
         # Memory dump by Frederik Teichert, http://teichert-ing.de, date: 2011.03.28
         # The Value Change Dump standard doesn't support multidimensional arrays so 
         # all memories are flattened and renamed.
@@ -177,20 +179,20 @@ def _writeVcdSigs(f, hierarchy, tracelists):
                     w = s._nrbits
                     if w:
                         if w == 1:
-                            print >> f, "$var reg 1 %s %s(%i) $end" % (s._code, n, memindex)
+                            print("$var reg 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
                         else:
-                            print >> f, "$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex)
+                            print("$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex), file=f)
                     else:
-                        print >> f, "$var real 1 %s %s(%i) $end" % (s._code, n, memindex)
+                        print("$var real 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
                     memindex += 1
     for i in range(curlevel):
-        print >> f, "$upscope $end"
+        print("$upscope $end", file=f)
-    print >> f
+    print(file=f)
-    print >> f, "$enddefinitions $end"
+    print("$enddefinitions $end", file=f)
-    print >> f, "$dumpvars"
+    print("$dumpvars", file=f)
     for s in siglist:
         s._printVcd() # initial value
-    print >> f, "$end"
+    print("$end", file=f)
             
             
         

myhdl/_tristate.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import warnings
 
 from myhdl._Signal import _Signal, _DelayedSignal

myhdl/_unparse.py

@@ -20,6 +20,7 @@
 """ unparse module
 
 """
+from __future__ import absolute_import
 
 
 import compiler

myhdl/_util.py

@@ -20,6 +20,8 @@
 """ Module with utilility objects for MyHDL.
 
 """
+from __future__ import absolute_import
+from __future__ import print_function
 
 
 import ast
@@ -36,7 +38,7 @@ def _printExcInfo():
     # msg = msg[msg.rindex('.')+1:]
     if str(value):
         msg += ": %s" % value
-        print >> sys.stderr, msg
+        print(msg, file=sys.stderr)
 
 _isGenFunc = inspect.isgeneratorfunction
 

myhdl/conversion/__init__.py

@@ -1,6 +1,7 @@
-from _verify import verify, analyze, registerSimulator
+from __future__ import absolute_import
-from _toVerilog import toVerilog
+from ._verify import verify, analyze, registerSimulator
-from _toVHDL import toVHDL
+from ._toVerilog import toVerilog
+from ._toVHDL import toVHDL
 
 __all__ = ["verify",
            "analyze",

myhdl/conversion/_analyze.py

@@ -20,6 +20,7 @@
 """ MyHDL conversion analysis module.
 
 """
+from __future__ import absolute_import
 
 import inspect
 # import compiler
@@ -42,7 +43,7 @@ from myhdl.conversion._misc import (_error, _access, _kind,
 from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode
 from myhdl._Signal import _Signal, _WaiterList
 from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal
-from myhdl._util import _isTupleOfInts, _dedent
+from myhdl._util import _isTupleOfInts, _dedent, _makeAST
 from myhdl._resolverefs import _AttrRefTransformer
 
 myhdlObjects = myhdl.__dict__.values()
@@ -76,13 +77,6 @@ def _makeName(n, prefixes, namedict):
 ##     print name
     return name
 
-def _makeAST(f):
-    s = inspect.getsource(f)
-    s = _dedent(s)
-    tree = ast.parse(s)
-    tree.sourcefile = inspect.getsourcefile(f)
-    tree.lineoffset = inspect.getsourcelines(f)[1]-1
-    return tree
 
 def _analyzeSigs(hierarchy, hdl='Verilog'):
     curlevel = 0
@@ -158,18 +152,13 @@ def _analyzeGens(top, absnames):
             tree = g
         elif isinstance(g, (_AlwaysComb, _AlwaysSeq, _Always)):
             f = g.func
-            s = inspect.getsource(f)
+            tree = _makeAST(f)
-            s = _dedent(s)
+            tree.symdict = f.__globals__.copy()
-            tree = ast.parse(s)
-            #print ast.dump(tree)
-            tree.sourcefile  = inspect.getsourcefile(f)
-            tree.lineoffset = inspect.getsourcelines(f)[1]-1
-            tree.symdict = f.func_globals.copy()
             tree.callstack = []
             # handle free variables
             tree.nonlocaldict = {}
-            if f.func_code.co_freevars:
+            if f.__code__.co_freevars:
-                for n, c in zip(f.func_code.co_freevars, f.func_closure):
+                for n, c in zip(f.__code__.co_freevars, f.__closure__):
                     obj = _cell_deref(c)
                     tree.symdict[n] = obj
                     # currently, only intbv as automatic nonlocals (until Python 3.0)
@@ -189,12 +178,7 @@ def _analyzeGens(top, absnames):
             v.visit(tree)
         else: # @instance
             f = g.gen.gi_frame
-            s = inspect.getsource(f)
+            tree = _makeAST(f)
-            s = _dedent(s)
-            tree = ast.parse(s)
-            # print ast.dump(tree)
-            tree.sourcefile = inspect.getsourcefile(f)
-            tree.lineoffset = inspect.getsourcelines(f)[1]-1
             tree.symdict = f.f_globals.copy()
             tree.symdict.update(f.f_locals)
             tree.nonlocaldict = {}
@@ -607,24 +591,18 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
             pass
         elif type(f) is FunctionType:
             argsAreInputs = False
-            s = inspect.getsource(f)
+            tree = _makeAST(f)
-            s = _dedent(s)
-            tree = ast.parse(s)
-            # print ast.dump(tree)
-            # print tree
             fname = f.__name__
             tree.name = _Label(fname)
-            tree.sourcefile = inspect.getsourcefile(f)
+            tree.symdict = f.__globals__.copy()
-            tree.lineoffset = inspect.getsourcelines(f)[1]-1
-            tree.symdict = f.func_globals.copy()
             tree.nonlocaldict = {}
             if fname in self.tree.callstack:
                 self.raiseError(node, _error.NotSupported, "Recursive call")
             tree.callstack = self.tree.callstack[:]
             tree.callstack.append(fname)
             # handle free variables
-            if f.func_code.co_freevars:
+            if f.__code__.co_freevars:
-                for n, c in zip(f.func_code.co_freevars, f.func_closure):
+                for n, c in zip(f.__code__.co_freevars, f.__closure__):
                     obj = _cell_deref(c)
                     if not  isinstance(obj, (int, long, _Signal)):
                         self.raiseError(node, _error.FreeVarTypeError, n)
@@ -769,7 +747,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
         self.kind = _kind.DECLARATION
         try:
             self.visit(node.elt)
-        except ConversionError, e:
+        except ConversionError as e:
             if e.kind == _error.UnboundLocal:
                 pass
             else:

myhdl/conversion/_misc.py

@@ -20,18 +20,16 @@
 """ myhdl toVerilog package.
 
 """
+from __future__ import absolute_import
 
 
 import inspect
-import compiler
-from compiler import ast as astNode
 import ast
 
 import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl._util import _flatten
-from myhdl._unparse import _unparse
 
 class _error(object):
     FirstArgType = "first argument should be a classic function"

myhdl/conversion/_toVHDL.py

@@ -20,6 +20,8 @@
 """ myhdl toVHDL conversion module.
 
 """
+from __future__ import absolute_import
+from __future__ import print_function
 
 
 import sys
@@ -125,7 +127,7 @@ class _ToVHDLConvertor(object):
 
         _converting = 1
         if self.name is None:
-            name = func.func_name
+            name = func.__name__
         else:
             name = str(self.name)
         try:
@@ -197,7 +199,7 @@ class _ToVHDLConvertor(object):
 
         if pfile:
             _writeFileHeader(pfile, ppath)
-            print >> pfile, _package
+            print(_package, file=pfile)
             pfile.close()
 
         _writeFileHeader(vfile, vpath)
@@ -258,45 +260,45 @@ def _writeFileHeader(f, fn):
                 date=datetime.today().ctime()
                 )
     if toVHDL.header:
-        print >> f, string.Template(toVHDL.header).substitute(vars)
+        print(string.Template(toVHDL.header).substitute(vars), file=f)
     if not toVHDL.no_myhdl_header:
-        print >> f, string.Template(myhdl_header).substitute(vars)
+        print(string.Template(myhdl_header).substitute(vars), file=f)
-    print >> f
+    print(file=f)
 
 
 def _writeCustomPackage(f, intf):
-    print >> f
+    print(file=f)
-    print >> f, "package pck_%s is" % intf.name
+    print("package pck_%s is" % intf.name, file=f)
-    print >> f
+    print(file=f)
-    print >> f, "attribute enum_encoding: string;"
+    print("attribute enum_encoding: string;", file=f)
-    print >> f
+    print(file=f)
     sortedList = list(_enumPortTypeSet)
     sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name))
     for t in sortedList:
-        print >> f, "    %s" % t._toVHDL()
+        print("    %s" % t._toVHDL(), file=f)
-    print >> f
+    print(file=f)
-    print >> f, "end package pck_%s;" % intf.name
+    print("end package pck_%s;" % intf.name, file=f)
-    print >> f
+    print(file=f)
 
 
 def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, numeric):
-    print >> f, "library IEEE;"
+    print("library IEEE;", file=f)
-    print >> f, "use IEEE.std_logic_1164.all;"
+    print("use IEEE.std_logic_1164.all;", file=f)
-    print >> f, "use IEEE.numeric_std.all;"
+    print("use IEEE.numeric_std.all;", file=f)
-    print >> f, "use std.textio.all;"
+    print("use std.textio.all;", file=f)
-    print >> f
+    print(file=f)
     if lib != "work":
-        print >> f, "library %s;" % lib
+        print("library %s;" % lib, file=f)
     if useClauses is not None:
         f.write(useClauses)
         f.write("\n")
     else:
-        print >> f, "use %s.pck_myhdl_%s.all;" % (lib, _shortversion)
+        print("use %s.pck_myhdl_%s.all;" % (lib, _shortversion), file=f)
-    print >> f
+    print(file=f)
     if needPck:
-        print >> f, "use %s.pck_%s.all;" % (lib, intf.name)
+        print("use %s.pck_%s.all;" % (lib, intf.name), file=f)
-        print >> f
+        print(file=f)
-    print >> f, "entity %s is" % intf.name
+    print("entity %s is" % intf.name, file=f)
     if intf.argnames:
         f.write("    port (")
         c = ''
@@ -326,11 +328,11 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, numeric):
                                   )
                 f.write("\n        %s: in %s%s" % (portname, p, r))
         f.write("\n    );\n")
-    print >> f, "end entity %s;" % intf.name
+    print("end entity %s;" % intf.name, file=f)
-    print >> f, doc
+    print(doc, file=f)
-    print >> f
+    print(file=f)
-    print >> f, "architecture %s of %s is" % (arch, intf.name)
+    print("architecture %s of %s is" % (arch, intf.name), file=f)
-    print >> f
+    print(file=f)
 
 
 def _writeFuncDecls(f):
@@ -385,7 +387,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
                               )
             # the following line implements initial value assignments
             # print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val))
-            print >> f, "signal %s: %s%s;" % (s._name, p, r)
+            print("signal %s: %s%s;" % (s._name, p, r), file=f)
         elif s._read:
             # the original exception
             # raise ToVHDLError(_error.UndrivenSignal, s._name)
@@ -394,7 +396,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
                           category=ToVHDLWarning
                           )
             constwires.append(s)
-            print >> f, "signal %s: %s%s;" % (s._name, p, r)
+            print("signal %s: %s%s;" % (s._name, p, r), file=f)
     for m in memlist:
         if not m._used:
             continue
@@ -409,16 +411,16 @@ def _writeSigDecls(f, intf, siglist, memlist):
         r = _getRangeString(m.elObj)
         p = _getTypeString(m.elObj)
         t = "t_array_%s" % m.name
-        print >> f, "type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
+        print("type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r), file=f)
-        print >> f, "signal %s: %s;" % (m.name, t)
+        print("signal %s: %s;" % (m.name, t), file=f)
-    print >> f
+    print(file=f)
 
 def _writeCompDecls(f,  compDecls):
     if compDecls is not None:
-        print >> f, compDecls
+        print(compDecls, file=f)
 
 def _writeModuleFooter(f, arch):
-    print >> f, "end architecture %s;" % arch
+    print("end architecture %s;" % arch, file=f)
 
 def _getRangeString(s):
     if isinstance(s._val, EnumItemType):
@@ -469,8 +471,8 @@ def _convertGens(genlist, siglist, memlist, vfile):
         v = Visitor(tree, blockBuf, funcBuf)
         v.visit(tree)
     vfile.write(funcBuf.getvalue()); funcBuf.close()
-    print >> vfile, "begin"
+    print("begin", file=vfile)
-    print >> vfile
+    print(file=vfile)
     for s in constwires:
         if s._type is bool:
             c = int(s._val)
@@ -485,19 +487,19 @@ def _convertGens(genlist, siglist, memlist, vfile):
                 pre, suf = "to_unsigned(", ", %s)" % w
         else:
             raise ToVHDLError("Unexpected type for constant signal", s._name)
-        print >> vfile, "%s <= %s%s%s;" % (s._name, pre, c, suf)
+        print("%s <= %s%s%s;" % (s._name, pre, c, suf), file=vfile)
-    print >> vfile
+    print(file=vfile)
     # shadow signal assignments
     for s in siglist:
         if hasattr(s, 'toVHDL') and s._read:
-            print >> vfile, s.toVHDL()
+            print(s.toVHDL(), file=vfile)
     # hack for slice signals in a list
     for m in memlist:
         if m._read:
             for s in m.mem:
                 if hasattr(s, 'toVHDL'):
-                    print >> vfile, s.toVHDL()
+                    print(s.toVHDL(), file=vfile)
-    print >> vfile
+    print(file=vfile)
     vfile.write(blockBuf.getvalue()); blockBuf.close()
 
 

myhdl/conversion/_toVHDLPackage.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #  This file is part of the myhdl library, a Python package for using
 #  Python as a Hardware Description Language.
 #

myhdl/conversion/_toVerilog.py

@@ -20,6 +20,8 @@
 """ myhdl toVerilog conversion module.
 
 """
+from __future__ import absolute_import
+from __future__ import print_function
 
 
 import sys
@@ -121,7 +123,7 @@ class _ToVerilogConvertor(object):
 
         _converting = 1
         if self.name is None:
-            name = func.func_name
+            name = func.__name__
         else:
             name = str(self.name)
         try:
@@ -214,24 +216,24 @@ def _writeFileHeader(f, fn, ts):
                 date=datetime.today().ctime()
                 )
     if not toVerilog.no_myhdl_header:
-        print >> f, string.Template(myhdl_header).substitute(vars)
+        print(string.Template(myhdl_header).substitute(vars), file=f)
     if toVerilog.header:
-        print >> f, string.Template(toVerilog.header).substitute(vars)
+        print(string.Template(toVerilog.header).substitute(vars), file=f)
-    print >> f
+    print(file=f)
-    print >> f, "`timescale %s" % ts
+    print("`timescale %s" % ts, file=f)
-    print >> f
+    print(file=f)
 
 
 def _writeModuleHeader(f, intf, doc):
-    print >> f, "module %s (" % intf.name
+    print("module %s (" % intf.name, file=f)
     b = StringIO()
     for portname in intf.argnames:
-        print >> b, "    %s," % portname
+        print("    %s," % portname, file=b)
-    print >> f, b.getvalue()[:-2]
+    print(b.getvalue()[:-2], file=f)
     b.close()
-    print >> f, ");"
+    print(");", file=f)
-    print >> f, doc
+    print(doc, file=f)
-    print >> f
+    print(file=f)
     for portname in intf.argnames:
         s = intf.argdict[portname]
         if s._name is None:
@@ -247,18 +249,18 @@ def _writeModuleHeader(f, intf, doc):
                 warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
                               category=ToVerilogWarning
                               )
-            print >> f, "output %s%s%s;" % (p, r, portname)
+            print("output %s%s%s;" % (p, r, portname), file=f)
             if s._driven == 'reg':
-                print >> f, "reg %s%s%s;" % (p, r, portname)
+                print("reg %s%s%s;" % (p, r, portname), file=f)
             else:
-                print >> f, "wire %s%s%s;" % (p, r, portname)
+                print("wire %s%s%s;" % (p, r, portname), file=f)
         else:
             if not s._read:
                 warnings.warn("%s: %s" % (_error.UnusedPort, portname),
                               category=ToVerilogWarning
                               )
-            print >> f, "input %s%s%s;" % (p, r, portname)
+            print("input %s%s%s;" % (p, r, portname), file=f)
-    print >> f
+    print(file=f)
 
 
 def _writeSigDecls(f, intf, siglist, memlist):
@@ -280,7 +282,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
                 k = 'reg'
             # the following line implements initial value assignments
             # print >> f, "%s %s%s = %s;" % (k, r, s._name, int(s._val))
-            print >> f, "%s %s%s%s;" % (k, p, r, s._name)
+            print("%s %s%s%s;" % (k, p, r, s._name), file=f)
         elif s._read:
             # the original exception
             # raise ToVerilogError(_error.UndrivenSignal, s._name)
@@ -289,8 +291,8 @@ def _writeSigDecls(f, intf, siglist, memlist):
                           category=ToVerilogWarning
                           )
             constwires.append(s)
-            print >> f, "wire %s%s;" % (r, s._name)
+            print("wire %s%s;" % (r, s._name), file=f)
-    print >> f
+    print(file=f)
     for m in memlist:
         if not m._used:
             continue
@@ -307,29 +309,29 @@ def _writeSigDecls(f, intf, siglist, memlist):
         k = 'wire'
         if m._driven:
             k = m._driven
-        print >> f, "%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth)
+        print("%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth), file=f)
-    print >> f
+    print(file=f)
     for s in constwires:
         if s._type in (bool, intbv):
             c = int(s.val)
         else:
             raise ToVerilogError("Unexpected type for constant signal", s._name)
-        print >> f, "assign %s = %s;" % (s._name, c)
+        print("assign %s = %s;" % (s._name, c), file=f)
-    print >> f
+    print(file=f)
     # shadow signal assignments
     for s in siglist:
         if hasattr(s, 'toVerilog') and s._read:
-            print >> f, s.toVerilog()
+            print(s.toVerilog(), file=f)
-    print >> f
+    print(file=f)
 
 
 def _writeModuleFooter(f):
-    print >> f, "endmodule"
+    print("endmodule", file=f)
 
 
 def _writeTestBench(f, intf, trace=False):
-    print >> f, "module tb_%s;" % intf.name
+    print("module tb_%s;" % intf.name, file=f)
-    print >> f
+    print(file=f)
     fr = StringIO()
     to = StringIO()
     pm = StringIO()
@@ -337,32 +339,32 @@ def _writeTestBench(f, intf, trace=False):
         s = intf.argdict[portname]
         r = _getRangeString(s)
         if s._driven:
-            print >> f, "wire %s%s;" % (r, portname)
+            print("wire %s%s;" % (r, portname), file=f)
-            print >> to, "        %s," % portname
+            print("        %s," % portname, file=to)
         else:
-            print >> f, "reg %s%s;" % (r, portname)
+            print("reg %s%s;" % (r, portname), file=f)
-            print >> fr, "        %s," % portname
+            print("        %s," % portname, file=fr)
-        print >> pm, "    %s," % portname
+        print("    %s," % portname, file=pm)
-    print >> f
+    print(file=f)
-    print >> f, "initial begin"
+    print("initial begin", file=f)
     if trace:
-        print >> f, '    $dumpfile("%s.vcd");' % intf.name
+        print('    $dumpfile("%s.vcd");' % intf.name, file=f)
-        print >> f, '    $dumpvars(0, dut);'
+        print('    $dumpvars(0, dut);', file=f)
     if fr.getvalue():
-        print >> f, "    $from_myhdl("
+        print("    $from_myhdl(", file=f)
-        print >> f, fr.getvalue()[:-2]
+        print(fr.getvalue()[:-2], file=f)
-        print >> f, "    );"
+        print("    );", file=f)
     if to.getvalue():
-        print >> f, "    $to_myhdl("
+        print("    $to_myhdl(", file=f)
-        print >> f, to.getvalue()[:-2]
+        print(to.getvalue()[:-2], file=f)
-        print >> f, "    );"
+        print("    );", file=f)
-    print >> f, "end"
+    print("end", file=f)
-    print >> f
+    print(file=f)
-    print >> f, "%s dut(" % intf.name
+    print("%s dut(" % intf.name, file=f)
-    print >> f, pm.getvalue()[:-2]
+    print(pm.getvalue()[:-2], file=f)
-    print >> f, ");"
+    print(");", file=f)
-    print >> f
+    print(file=f)
-    print >> f, "endmodule"
+    print("endmodule", file=f)
 
 
 def _getRangeString(s):

myhdl/conversion/_verify.py

@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import sys
 import os
 import tempfile
@@ -103,8 +105,8 @@ class  _VerificationClass(object):
     def __call__(self, func, *args, **kwargs):
 
         vals = {}
-        vals['topname'] = func.func_name
+        vals['topname'] = func.__name__
-        vals['unitname'] = func.func_name.lower()
+        vals['unitname'] = func.__name__.lower()
         vals['version'] = _version
 
         hdlsim = self.simulator
@@ -143,11 +145,11 @@ class  _VerificationClass(object):
         #print(analyze)
         ret = subprocess.call(analyze, shell=True)
         if ret != 0:
-            print >> sys.stderr, "Analysis failed"
+            print("Analysis failed", file=sys.stderr)
             return ret
 
         if self._analyzeOnly:
-            print >> sys.stderr, "Analysis succeeded"
+            print("Analysis succeeded", file=sys.stderr)
             return 0
 
         f = tempfile.TemporaryFile()
@@ -161,7 +163,7 @@ class  _VerificationClass(object):
         flines = f.readlines()
         f.close()
         if not flines:
-            print >> sys.stderr, "No MyHDL simulation output - nothing to verify"
+            print("No MyHDL simulation output - nothing to verify", file=sys.stderr)
             return 1
 
 
@@ -169,7 +171,7 @@ class  _VerificationClass(object):
             #print(elaborate)
             ret = subprocess.call(elaborate, shell=True)
             if ret != 0:
-                print >> sys.stderr, "Elaboration failed"
+                print("Elaboration failed", file=sys.stderr)
                 return ret
             
         g = tempfile.TemporaryFile()
@@ -214,9 +216,9 @@ class  _VerificationClass(object):
         d.close()
 
         if not s:
-            print >> sys.stderr, "Conversion verification succeeded"
+            print("Conversion verification succeeded", file=sys.stderr)
         else:
-            print >> sys.stderr, "Conversion verification failed"
+            print("Conversion verification failed", file=sys.stderr)
             # print >> sys.stderr, s ,
             return 1
 

myhdl/test/benchmark/convert.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_lfsr24 import test_lfsr24

myhdl/test/benchmark/glibc_random.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 

myhdl/test/benchmark/lfsr24.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def lfsr24(lfsr, enable, clock, reset):

myhdl/test/benchmark/long_divider.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def long_divider(

myhdl/test/benchmark/random_generator.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def random_generator(random_word, enable, clock, reset):

myhdl/test/benchmark/test_findmax.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from glibc_random import glibc_random

myhdl/test/benchmark/test_findmax_sigs.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from glibc_random import glibc_random

myhdl/test/benchmark/test_lfsr24.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from lfsr24 import lfsr24

myhdl/test/benchmark/test_longdiv.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from glibc_random import glibc_random

myhdl/test/benchmark/test_longdiv_10.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_11.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_12.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_13.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_14.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_15.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_16.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_17.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_18.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_longdiv_9.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from test_longdiv import test_longdiv

myhdl/test/benchmark/test_randgen.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from random_generator import random_generator

myhdl/test/benchmark/test_timer.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from timer import timer_sig, timer_var

myhdl/test/benchmark/test_timer_array.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 from timer import timer_sig, timer_var

myhdl/test/benchmark/timer.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def timer_sig(flag, clock, reset, MAXVAL):

myhdl/test/bugs/GHDL.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify
 
 verify.simulator = "GHDL"

myhdl/test/bugs/cver.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify
 
 verify.simulator = "cver"

myhdl/test/bugs/icarus.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify
 
 verify.simulator = "icarus"

myhdl/test/bugs/test_bug_1740778.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1835792.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1835797.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1837003.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
@@ -25,7 +26,7 @@ yin = Signal(bool(0))
 def test_bug_1837003():
     try:
         toVerilog(SubFunction,xout,yout,x,y)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.ShadowingVar
     else:
         assert False

myhdl/test/bugs/test_bug_28.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def bug_28(dout, channel):

myhdl/test/bugs/test_bug_3529686.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def bug_3529686(clr, clk, run, ack, serialout):

myhdl/test/bugs/test_bug_3577799.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_bug_39.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_42.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #! /usr/bin/env python
 
 from myhdl import *

myhdl/test/bugs/test_bug_42_2.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #! /usr/bin/env python
 
 from myhdl import *

myhdl/test/bugs/test_bug_43.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #! /usr/bin/env python
 
 from myhdl import *

myhdl/test/bugs/test_bug_44.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 WIDTH=4

myhdl/test/bugs/test_bug_aj1s.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_boolconst.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 INT_CONDITION_0 = 0 

myhdl/test/bugs/test_bug_boolop.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def gray_counter (clk, reset, enable, gray_count):

myhdl/test/bugs/test_bug_enum_toVHDL.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 #t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')

myhdl/test/bugs/test_bug_enum_toVHDL_2.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')

myhdl/test/bugs/test_issue_10.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 #!/usr/bin/python2.7-32
 # -*- coding: utf-8 -*-
 

myhdl/test/bugs/test_issue_10_2.py

@@ -2,6 +2,7 @@
 # -*- coding: utf-8 -*-
 """Failed VHDL code example
 """
+from __future__ import absolute_import
 
 from myhdl import *
 from myhdl.conversion import verify

myhdl/test/bugs/test_issue_13.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_issue_9.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def issue_9():

myhdl/test/bugs/vcom.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "vcom"

myhdl/test/bugs/vlog.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "vlog"

myhdl/test/conversion/general/GHDL.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "GHDL"

myhdl/test/conversion/general/cver.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "cver"

myhdl/test/conversion/general/icarus.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl.conversion import verify, analyze
 
 verify.simulator = analyze.simulator = "icarus"

myhdl/test/conversion/general/test_ShadowSignal.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def bench_SliceSignal():

myhdl/test/conversion/general/test_adapter.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def adapter(o_err, i_err, o_spec, i_spec):

myhdl/test/conversion/general/test_bin2gray.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_case.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def map_case4(z, a):

myhdl/test/conversion/general/test_constants.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 
 def constants(v, u, x, y, z, a):

myhdl/test/conversion/general/test_dec.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 import random

myhdl/test/conversion/general/test_errors.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
@@ -15,7 +16,7 @@ def test_SigAugmAssignUnsupported():
     a = Signal(intbv(0)[8:])
     try:
         verify(sigAugmAssignUnsupported, z, a)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.NotSupported
     else:
         assert False
@@ -34,7 +35,7 @@ def test_modbvRange():
     b = Signal(intbv(0)[4:])
     try:
         verify(modbvRange, z, a, b)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.ModbvRange
     else:
         assert False
@@ -51,7 +52,7 @@ def test_modbvSigRange():
     b = Signal(intbv(0)[4:])
     try:
         verify(modbvSigRange, z, a, b)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.ModbvRange
     else:
         assert False

myhdl/test/conversion/general/test_fsm.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_hec.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange

myhdl/test/conversion/general/test_inc.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/conversion/general/test_intbv_signed.py

@@ -19,6 +19,7 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Run the intbv.signed() unit tests. """
+from __future__ import absolute_import
 
 from myhdl import *
 

myhdl/test/conversion/general/test_interfaces1.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 
 import sys
 

myhdl/test/conversion/general/test_interfaces2.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 
 import sys
 

myhdl/test/conversion/general/test_interfaces3.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 
 import sys
 

myhdl/test/conversion/general/test_listofsigs.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
@@ -298,7 +299,7 @@ def test_portInList():
 
     try:
         inst = conversion.analyze(portInList, z, a, b)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.PortInList
     else:
         assert False
@@ -323,7 +324,7 @@ def test_sigInMultipleLists():
 
     try:
         inst = conversion.analyze(sigInMultipleLists)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.SignalInMultipleLists
     else:
         assert False
@@ -344,7 +345,7 @@ def test_listAsPort():
     outp = [Signal(intbv(0)[8:0]) for index in range(count)]
     try:
         inst = conversion.analyze(my_register, clk, inp, outp)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.ListAsPort
     else:
         assert False

myhdl/test/conversion/general/test_loops.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange
@@ -344,7 +345,7 @@ def testWhileBreakContinueLoop():
 def testForLoopError1():
     try:
         analyze(LoopBench, ForLoopError1)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.Requirement
     else:
         assert False
@@ -352,7 +353,7 @@ def testForLoopError1():
 def testForLoopError2():
     try:
         analyze(LoopBench, ForLoopError2)
-    except ConversionError, e:
+    except ConversionError as e:
         assert e.kind == _error.Requirement
     else:
         assert False

myhdl/test/conversion/general/test_method.py

@@ -1,3 +1,4 @@
+from __future__ import absolute_import
 import sys
 from myhdl import *
 from myhdl.conversion import verify
@@ -105,7 +106,7 @@ def ObjBench(hObj):
         hdlobj_inst = hObj()
         hdl_inst = hdlobj_inst.method_func(clk, srst, x, y)
     else:
-        raise StandardError, "Incorrect hOjb %s" % (type(hObj), str(hObj))
+        raise StandardError("Incorrect hOjb %s" % (type(hObj), str(hObj)))
 
 
     @instance