From 4ca0992ec2a83ae5583cd9f6cf3d70e8974c5830 Mon Sep 17 00:00:00 2001 From: jand Date: Mon, 19 Dec 2005 11:25:14 +0000 Subject: [PATCH] spell --- doc/manual/conversion.tex | 22 +++++++++++----------- doc/manual/intro.tex | 10 +++++----- doc/manual/modeling.tex | 2 +- doc/manual/reference.tex | 4 ++-- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/doc/manual/conversion.tex b/doc/manual/conversion.tex index 27afffd7..ee7be0d7 100644 --- a/doc/manual/conversion.tex +++ b/doc/manual/conversion.tex @@ -87,12 +87,12 @@ The Verilog converter generates the appropriate code. \subsection{Support for RAM inference \label{conf-features-ram}} Certain synthesis tools can map Verilog memories to RAM -structures. To support this interesting feature, the Verilog convertor +structures. To support this interesting feature, the Verilog converter maps lists of signals to Verilog memories. \subsection{Support for ROM memory \label{conf-features-rom}} Some synthesis tools can infer a ROM -from a case statement. The Verilog convertor does the expansion into +from a case statement. The Verilog converter does the expansion into a case statement automatically, based on a higher level description. The rom access is described in a single line, by indexing into a tuple of integers. @@ -106,7 +106,7 @@ and the user has to declare signed variables explicitly. When the two representations are mixed in an expression, all operands are interpreted as unsigned, which typically leads to unexpected results. -The Verilog convertor handles negative \code{intbv} objects by using +The Verilog converter handles negative \code{intbv} objects by using signed Verilog representation. Also, it automatically performs sign extension and casting to a signed representation when unsigned numbers are used in a mixed expression. In this way, it automates a task which @@ -179,7 +179,7 @@ and maximum values, e.g. as follows: index = intbv(0, min=MIN, max=MAX) \end{verbatim} -The Verilog convertor supports \class{intbv} objects that +The Verilog converter supports \class{intbv} objects that can take negative values. Alternatively, a slice can be taken from an \class{intbv} object @@ -466,8 +466,8 @@ from the MyHDL design. \subsection{A small combinatorial design\label{conv-usage-comb}} -The second example is a small combinatoriaol design, more -specifically the binary to Gray code convertor from previous chapters: +The second example is a small combinatorial design, more +specifically the binary to Gray code converter from previous chapters: \begin{verbatim} def bin2gray(B, G, width): @@ -528,7 +528,7 @@ endmodule \end{verbatim} \subsection{A hierarchical design\label{conv-usage-hier}} -The Verilog convertor can handle designs with an +The Verilog converter can handle designs with an arbitrarily deep hierarchy. For example, suppose we want to design an @@ -796,7 +796,7 @@ endmodule \subsection{RAM inference \label{conf-usage-RAM}} Certain synthesis tools can map Verilog memories to RAM -structures. To support this interesting feature, the Verilog convertor +structures. To support this interesting feature, the Verilog converter maps lists of signals in MyHDL to Verilog memories. The following MyHDL example is a ram model that uses a list of signals @@ -856,7 +856,7 @@ endmodule \subsection{ROM inference \label{conf-usage-ROM}} Some synthesis tools can infer a ROM memory from a case statement. The -Verilog convertor can perform the expansion into a case statement +Verilog converter can perform the expansion into a case statement automatically, based on a higher level description. The ROM access is described in a single line, by indexing into a tuple of integers. The tuple can be described manually, but also by programmatical @@ -916,7 +916,7 @@ endmodule MyHDL provides a way a method to include user-defined Verilog code during the conversion process. -MyHDL defines a hook that is understood by the convertor but ignored by +MyHDL defines a hook that is understood by the converter but ignored by the simulator. The hook is called \code{__verilog__}. It operates like a special return value. When a MyHDL function defines \code{__verilog__}, the Verilog converter will use its value instead of the @@ -972,7 +972,7 @@ that the format specifier indicator \% needs to be escaped (by doubling it) if it is required in the user-defined code. There is one more issue that needs user attention. Normally, the -Verilog convertor infers inputs, internal signals, and outputs. It +Verilog converter infers inputs, internal signals, and outputs. It also detects undriven and multiple driven signals. To do this, it assumes that signals are not driven by default. It then processes the code to find out which signals are driven from where. However, it diff --git a/doc/manual/intro.tex b/doc/manual/intro.tex index 7930c458..5529f6be 100644 --- a/doc/manual/intro.tex +++ b/doc/manual/intro.tex @@ -126,7 +126,7 @@ sim.run(50) The clock driver function \function{ClkDriver} has a clock signal as its parameter. This is how a -\emph{port} is modelled in MyHDL. The function +\emph{port} is modeled in MyHDL. The function defines a generator that continuously toggles a clock signal after a certain delay. A new value of a signal is specified by assigning to its @@ -172,7 +172,7 @@ modules. We have also seen that ports are modeled by using signals as parameters. To make designs reusable we will also want to use other objects as parameters. For example, we can change the clock generator function to make it more general -and reusable, by making the clock period parametrizable, as +and reusable, by making the clock period parameterizable, as follows: \begin{verbatim} @@ -238,7 +238,7 @@ We can create any number of instances by calling the functions with the appropriate parameters. Hierarchy can be modeled by defining the instances in a higher-level function, and returning them. This pattern can be repeated for an arbitrary number of -hierarhical levels. Consequently, the general definition +hierarchical levels. Consequently, the general definition of a \myhdl\ \dfn{instance} is recursive: an instance \index{instance!defined}% is either a sequence of instances, or a generator. @@ -253,9 +253,9 @@ def greetings(): clk2 = Signal(0) clkdriver_1 = ClkDriver(clk1) # positional and default association - clkdriver_2 = ClkDriver(clk=clk2, period=19) # named assocation + clkdriver_2 = ClkDriver(clk=clk2, period=19) # named association hello_1 = Hello(clk=clk1) # named and default association - hello_2 = Hello(to="MyHDL", clk=clk2) # named assocation + hello_2 = Hello(to="MyHDL", clk=clk2) # named association return clkdriver_1, clkdriver_2, hello_1, hello_2 diff --git a/doc/manual/modeling.tex b/doc/manual/modeling.tex index d96696d1..bc7ed200 100644 --- a/doc/manual/modeling.tex +++ b/doc/manual/modeling.tex @@ -571,7 +571,7 @@ point for experiments and exploration. Over time, more techniques that prove useful will be added. \end{quote} -\subsection{Modelling with bus-functional procedures \label{model-bfm}} +\subsection{Modeling with bus-functional procedures \label{model-bfm}} \index{bus-functional procedure}% A \dfn{bus-functional procedure} is a reusable encapsulation of the diff --git a/doc/manual/reference.tex b/doc/manual/reference.tex index bac7fa1d..e1c318e2 100644 --- a/doc/manual/reference.tex +++ b/doc/manual/reference.tex @@ -67,7 +67,7 @@ This attribute is used to overwrite the default basename for the VCD output filename. \end{memberdesc} -\section{Modelling \label{ref-model}} +\section{Modeling \label{ref-model}} \subsection{The \class{Signal} class \label{ref-sig}} \declaremodule{}{myhdl} @@ -124,7 +124,7 @@ is supposed to be driven from the MyHDL code, and how it should be declared in Verilog after conversion. The allowed values are \code{'reg'} and \code{'wire'}. -This attribute is useful when the Verilog convertor cannot +This attribute is useful when the Verilog converter cannot infer automatically whether and how a signal is driven. This occurs when the signal is driven from user-defined Verilog code. \end{memberdesc}