prefer case over casez if possible

myhdl/conversion/_analyze.py

@@ -1091,6 +1091,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
             choices.add(item)
         node.isCase = True
         node.caseVar = var1
+        node.caseItem = item1
         if (len(choices) == len(var1.obj)) or (node.else_ is not None):
             node.isFullCase = True
 

myhdl/conversion/_toVerilog.py

@@ -1258,7 +1258,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
 #        if node.isFullCase:
 #            self.write(" full_case")
 #        self.writeline()
-        self.write("casez (")
+        caseType = "case"
+        if isinstance(node.caseItem, EnumItemType):
+            if node.caseItem._type._encoding in ('one_hot', 'one_cold'):
+                caseType = "casez"
+        self.write("%s (" % caseType)
         self.visit(var)
         self.write(")")
         self.indent()