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prefer case over casez if possible

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This commit is contained in:
Jan Decaluwe 2010-07-21 13:11:28 +02:00
parent b69ace1b99
commit 4e8ccc15a3
2 changed files with 6 additions and 1 deletions
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1
myhdl/conversion/_analyze.py
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@ -1091,6 +1091,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
choices.add(item) choices.add(item)
node.isCase = True node.isCase = True
node.caseVar = var1 node.caseVar = var1
node.caseItem = item1
if (len(choices) == len(var1.obj)) or (node.else_ is not None): if (len(choices) == len(var1.obj)) or (node.else_ is not None):
node.isFullCase = True node.isFullCase = True

6
myhdl/conversion/_toVerilog.py
View File

@ -1258,7 +1258,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
# if node.isFullCase: # if node.isFullCase:
# self.write(" full_case") # self.write(" full_case")
# self.writeline() # self.writeline()
self.write("casez (") caseType = "case"
if isinstance(node.caseItem, EnumItemType):
if node.caseItem._type._encoding in ('one_hot', 'one_cold'):
caseType = "casez"
self.write("%s (" % caseType)
self.visit(var) self.visit(var)
self.write(")") self.write(")")
self.indent() self.indent()