detect variable names that shadow Signal names

myhdl/conversion/_analyze.py

@@ -449,6 +449,8 @@ class _AnalyzeVisitor(_ConversionMixin):
             self.visit(expr, _access.INPUT, _kind.DECLARATION)
             node.kind = _kind.DECLARATION
             n = target.name
+            if n in self.ast.sigdict:
+                self.raiseError(node, _error.ShadowingVar)
             obj = self.getObj(expr)
             if obj is None:
                 self.raiseError(node, _error.TypeInfer, n)

myhdl/conversion/_misc.py

@@ -58,6 +58,7 @@ _error.ReturnNrBitsMismatch = "Returned nr of bits mismatch"
 _error.ReturnIntbvBitWidth = "Returned intbv instance should have bit width"
 _error.ReturnTypeInfer = "Can't infer return type"
 _error.ShadowingSignal = "Port is shadowed by internal signal"
+_error.ShadowingVar = "Variable has same name as a hierarchical Signal"
 _error.FreeVarTypeError = "Free variable should be a Signal or an int"
 _error.ExtraArguments = "Extra positional or named arguments are not supported"
 _error.UnsupportedYield = "Unsupported yield statement"

myhdl/test/bugs/test_bug_1837003.py

@@ -0,0 +1,31 @@
+from myhdl import *
+from myhdl import ConversionError
+from myhdl.conversion._misc import _error
+
+def SubFunction(xout,yout,xin,yin):
+    @always_comb
+    def logic():
+        x = 4
+        y = 2
+        xout.next = xin
+        yout.next = yin
+    return instances()
+
+
+def Function(xout,yout,x,y):
+    return SubFunction(xout,yout,x,y)
+
+x = Signal(bool(0))
+y = Signal(bool(0))
+xout = Signal(bool(0))
+yout = Signal(bool(0))
+xin = Signal(bool(0))
+yin = Signal(bool(0))
+
+def test_bug_1837003():
+    try:
+        toVerilog(SubFunction,xout,yout,x,y)
+    except ConversionError, e:
+        assert e.kind == _error.ShadowingVar
+    else:
+        assert False