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some robustness tests

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jand 2003-05-14 16:41:11 +00:00
parent 285b40f59e
commit 4ee436f37c
2 changed files with 5 additions and 0 deletions
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4
cosimulation/icarus/myhdl.c
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@ -274,6 +274,10 @@ static PLI_INT32 readonly_callback(p_cb_data cb_data)
verilog_time_s.type = vpiSimTime;
vpi_get_time(NULL, &verilog_time_s);
verilog_time = timestruct_to_time(&verilog_time_s);
if (verilog_time != (pli_time * 1000 + delta)) {
vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low );
vpi_printf("%llu %llu %d", verilog_time, pli_time, delta);
}
assert(verilog_time == pli_time * 1000 + delta);
sprintf(buf, "%llu ", pli_time);
net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle);

1
cosimulation/icarus/test/test_all.py
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@ -30,6 +30,7 @@ sys.path.append("../../test")
import test_bin2gray, test_inc, test_dff
modules = (test_dff, )
modules = (test_inc, )
modules = (test_bin2gray, test_inc, test_dff )
import unittest