From 4ee436f37c4013154c40349472d21152eea092e3 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Wed, 14 May 2003 16:41:11 +0000
Subject: [PATCH] some robustness tests

---
 cosimulation/icarus/myhdl.c          | 4 ++++
 cosimulation/icarus/test/test_all.py | 1 +
 2 files changed, 5 insertions(+)

diff --git a/cosimulation/icarus/myhdl.c b/cosimulation/icarus/myhdl.c
index ab9e4436..0428b12f 100644
--- a/cosimulation/icarus/myhdl.c
+++ b/cosimulation/icarus/myhdl.c
@@ -274,6 +274,10 @@ static PLI_INT32 readonly_callback(p_cb_data cb_data)
   verilog_time_s.type = vpiSimTime;
   vpi_get_time(NULL, &verilog_time_s);
   verilog_time = timestruct_to_time(&verilog_time_s);
+  if (verilog_time != (pli_time * 1000 + delta)) {
+    vpi_printf("%u %u\n", verilog_time_s.high, verilog_time_s.low );
+    vpi_printf("%llu %llu %d", verilog_time, pli_time, delta);
+  } 
   assert(verilog_time == pli_time * 1000 + delta);
   sprintf(buf, "%llu ", pli_time);
   net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle);
diff --git a/cosimulation/icarus/test/test_all.py b/cosimulation/icarus/test/test_all.py
index 5e3a6455..bebca671 100644
--- a/cosimulation/icarus/test/test_all.py
+++ b/cosimulation/icarus/test/test_all.py
@@ -30,6 +30,7 @@ sys.path.append("../../test")
 import test_bin2gray, test_inc, test_dff
 
 modules = (test_dff, )
+modules = (test_inc,  )
 modules = (test_bin2gray, test_inc, test_dff )
 
 import unittest