mirror of
https://github.com/myhdl/myhdl.git
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Merge branch 'jck-travis'
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commit
51766a3c89
@ -8,6 +8,10 @@ before_install:
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- if [ $CI_TARGET == "icarus" ]; then
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sudo apt-get update -qq;
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sudo apt-get install -y iverilog;
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elif [ $CI_TARGET == "ghdl" ]; then
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sudo apt-add-repository -y ppa:pgavin/ghdl;
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sudo apt-get update -qq;
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sudo apt-get install -y ghdl;
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fi
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install:
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@ -16,6 +20,7 @@ install:
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env:
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- CI_TARGET=core
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- CI_TARGET=icarus
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- CI_TARGET=ghdl
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script: ./ci.sh
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103
ci.sh
103
ci.sh
@ -1,19 +1,98 @@
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#!/bin/bash
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# {{{ Utilities
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# {{{ cfont
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cfont() {
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while (($#!=0))
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do
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case $1 in
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-b) echo -ne " " ;;
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-t) echo -ne "\t";;
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-n) echo -ne "\n";;
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-black) echo -ne "\033[30m";;
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-red) echo -ne "\033[31m";;
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-green) echo -ne "\033[32m";;
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-yellow) echo -ne "\033[33m";;
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-blue) echo -ne "\033[34m";;
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-purple) echo -ne "\033[35m";;
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-cyan) echo -ne "\033[36m";;
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-white|-gray) echo -ne "\033[37m";;
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-reset) echo -ne "\033[0m";;
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-h|-help|--help)
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echo "Usage: cfont -color1 message1 -color2 message2 ...";
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echo "eg: cfont -red [ -blue message1 message2 -red ]";
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;;
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*)
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echo -ne "$1"
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;;
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esac
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shift
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done
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}
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# }}}
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# {{{ print_heading
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print_heading() {
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msg="$@"
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line=$(printf '%0.1s' "="{1..80})
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lPad=$(( ( 80 - ${#msg} ) / 2 - 1 ))
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[[ $lPad -lt 0 ]] && lPad=0
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pad="${line::$lPad}"
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cfont -cyan
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echo $line
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echo $pad $msg $pad
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echo $line
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cfont -reset
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}
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# }}}
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# {{{ run_test
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run_test() {
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cfont -cyan; echo "running test: $command $@" ; cfont -n -reset
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$command "$@"
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if [ $? -ne 0 ]; then
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cfont -red; echo "test failed: $command $@" ; cfont -n -reset
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foundError=1
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else
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cfont -green "OK" -n -reset
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fi
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}
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# }}}
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# }}}
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foundError=0
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echo "Running $CI_TARGET tests"
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CI_TARGET=${CI_TARGET:-core}
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if [ "$CI_TARGET" == "core" ]; then
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make -C myhdl/test/core
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make -C myhdl/test/core2
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elif [ "$CI_TARGET" == "icarus" ]; then
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echo "======================================================================="
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echo "=========== A. Test Converted Verilog Code ========="
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echo "======================================================================="
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make -C "myhdl/test/conversion/general" icarus
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echo "======================================================================="
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echo "=========== B. Test Co-Simulation with Converted Verilog Code ========="
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echo "======================================================================="
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make -C cosimulation/icarus
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make -C myhdl/test/conversion/toVerilog
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print_heading "Core MyHDL Testbench"
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run_test make -C myhdl/test/core
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run_test make -C myhdl/test/core2
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elif [ "$CI_TARGET" == "icarus" ]; then
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print_heading "Test Converted Verilog Code"
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run_test make -C "myhdl/test/conversion/general" icarus
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print_heading "Test Co-Simulation with Converted Verilog Code"
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run_test make -C cosimulation/icarus
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run_test make -C myhdl/test/conversion/toVerilog
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elif [ "$CI_TARGET" == "ghdl" ]; then
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print_heading "Test Converted VHDL Code"
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run_test make -C "myhdl/test/conversion/general" GHDL
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print_heading "Test Co-Simulation with Converted VHDL Code"
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run_test make -C myhdl/test/conversion/toVHDL GHDL
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fi
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exit $foundError
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@ -36,16 +36,16 @@ def bench_ConcatSignal():
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s = ConcatSignal(a, b, c, d)
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I = 2**len(a)
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J = 2**len(b)
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K = 2**len(c)
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M = 2**len(d)
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I_max = 2**len(a)
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J_max = 2**len(b)
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K_max = 2**len(c)
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M_max = 2**len(d)
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@instance
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def check():
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for i in range(I):
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for j in range(J):
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for k in range(K):
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for m in range(M):
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for i in range(I_max):
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for j in range(J_max):
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for k in range(K_max):
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for m in range(M_max):
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a.next = i
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b.next = j
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c.next = k
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