mirror of
https://github.com/myhdl/myhdl.git
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Version number 0.7
This commit is contained in:
Jan Decaluwe
parent
e95044322d
commit
52814f1eb3
@ -1,6 +1,9 @@
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0.7dev
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======
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Release 0.7 21-Dec-2010
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-----------------------
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Full details about new features and changes can be found here:
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http://www.myhdl.org/doc/0.7/whatsnew/0.7.html
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Release 0.6 9-Jan-2009
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-----------------------
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11
README.txt
11
README.txt
@ -1,5 +1,5 @@
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MyHDL 0.7dev
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============
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MyHDL 0.7
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=========
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What is MyHDL?
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--------------
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@ -22,13 +22,13 @@ Documentation
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-------------
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The manual is available on-line:
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http://www.myhdl.org/doc/0.6/manual
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http://www.myhdl.org/doc/0.7/manual
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What's new
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----------
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To find out what's new in this release, please read:
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http://www.myhdl.org/doc/0.6/whatsnew/0.6.html
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http://www.myhdl.org/doc/0.7/whatsnew/0.7.html
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Installation
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------------
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@ -48,7 +48,8 @@ In this case, be sure to add the appropriate install dir to the
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$PYTHONPATH.
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If necessary, consult the distutils documentation in the standard
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Python library if necessary for more details; or contact me.
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Python library if necessary for more details;
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or contact me.
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You can test the proper installation as follows:
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@ -40,9 +40,9 @@ copyright = '2008-2010, Jan Decaluwe'
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# other places throughout the built documents.
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#
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# The short X.Y version.
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version = '0.7dev'
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version = '0.7'
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# The full version, including alpha/beta/rc tags.
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release = '0.7dev'
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release = '0.7'
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# There are two options for replacing |today|: either, you set today to some
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# non-false value, then it is used:
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@ -122,7 +122,8 @@ latex_font_size = '11pt'
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# Grouping the document tree into LaTeX files. List of tuples
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# (source start file, target name, title, author, document class [howto/manual]).
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latex_documents = [('manual/index', 'MyHDL.tex', 'MyHDL manual', 'Jan Decaluwe', 'manual'),
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('whatsnew/0.6', 'whatsnew0.6.tex', 'What\'s new in MyHDL 0.6', 'Jan Decaluwe', 'manual')
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('whatsnew/0.6', 'whatsnew0.6.tex', 'What\'s new in MyHDL 0.6', 'Jan Decaluwe', 'howto'),
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('whatsnew/0.7', 'whatsnew0.7.tex', 'What\'s new in MyHDL 0.7', 'Jan Decaluwe', 'howto'),
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]
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# Additional stuff for the LaTeX preamble.
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@ -1,6 +1,6 @@
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// File: FramerCtrl.v
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// Generated by MyHDL 0.7dev
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// Date: Sun Oct 10 21:39:53 2010
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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@ -1,6 +1,6 @@
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-- File: FramerCtrl.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Sun Oct 10 21:39:53 2010
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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@ -20,7 +20,7 @@ use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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use work.pck_myhdl_07.all;
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use work.pck_FramerCtrl.all;
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@ -1,6 +1,6 @@
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// File: GrayIncReg.v
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// Generated by MyHDL 0.7dev
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// Date: Sun Oct 10 21:39:52 2010
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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@ -1,6 +1,6 @@
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-- File: GrayIncReg.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Sun Oct 10 21:39:52 2010
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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library IEEE;
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@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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use work.pck_myhdl_07.all;
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entity GrayIncReg is
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port (
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// File: Inc.v
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// Generated by MyHDL 0.7dev
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// Date: Sun Oct 10 21:39:52 2010
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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@ -1,6 +1,6 @@
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-- File: Inc.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Sun Oct 10 21:39:52 2010
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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library IEEE;
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@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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use work.pck_myhdl_07.all;
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entity Inc is
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port (
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// File: bin2gray.v
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// Generated by MyHDL 0.7dev
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// Date: Sun Oct 10 21:39:52 2010
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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-- File: bin2gray.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Sun Oct 10 21:39:52 2010
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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library IEEE;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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use work.pck_myhdl_07.all;
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entity bin2gray is
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port (
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// File: inc_comb.v
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// Generated by MyHDL 0.7dev
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// Date: Fri Dec 17 11:39:33 2010
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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-- File: inc_comb.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Fri Dec 17 11:39:33 2010
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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library IEEE;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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use work.pck_myhdl_07.all;
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entity inc_comb is
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port (
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@ -1,12 +1,13 @@
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-- File: pck_myhdl_07dev.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Fri Jul 2 13:23:50 2010
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-- File: pck_myhdl_07.vhd
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-- Generated by MyHDL 0.7
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package pck_myhdl_07dev is
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package pck_myhdl_07 is
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attribute enum_encoding: string;
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@ -36,10 +37,10 @@ package pck_myhdl_07dev is
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function "-" (arg: unsigned) return signed;
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end pck_myhdl_07dev;
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end pck_myhdl_07;
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package body pck_myhdl_07dev is
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package body pck_myhdl_07 is
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function to_std_logic (arg: boolean) return std_logic is
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begin
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return - signed(resize(arg, arg'length+1));
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end function "-";
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end pck_myhdl_07dev;
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end pck_myhdl_07;
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@ -1,6 +1,6 @@
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-- File: ram.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Sun Oct 10 21:39:53 2010
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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library IEEE;
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@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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use work.pck_myhdl_07.all;
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entity ram is
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port (
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// File: ram_1.v
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// Generated by MyHDL 0.7dev
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// Date: Sun Oct 10 21:39:53 2010
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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// File: rom.v
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// Generated by MyHDL 0.7dev
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// Date: Sun Oct 10 21:39:53 2010
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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-- File: rom.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Sun Oct 10 21:39:53 2010
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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library IEEE;
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@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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use work.pck_myhdl_07.all;
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entity rom is
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port (
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@ -46,7 +46,7 @@ toVerilog -- function that converts a design to Verilog
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"""
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__version__ = "0.7dev"
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__version__ = "0.7"
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import sys
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import warnings
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6
setup.py
6
setup.py
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from distutils.core import setup
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classifiers = """\
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Development Status :: 3 - Alpha
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Development Status :: 4 - Beta
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Intended Audience :: Developers
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License :: OSI Approved :: GNU Library or Lesser General Public License (LGPL)
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Operating System :: OS Independent
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@ -32,12 +32,12 @@ Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
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setup(name="myhdl",
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version="0.7dev",
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version="0.7",
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description="Python as a Hardware Description Language",
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long_description = "See home page.",
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author="Jan Decaluwe",
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author_email="jan@jandecaluwe.com",
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url="http://jandecaluwe.com/Tools/MyHDL/Overview.html",
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url="http://www.myhdl.org",
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download_url="http://sourceforge.net/project/showfiles.php?group_id=91207",
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packages=['myhdl', 'myhdl.conversion'],
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license="LGPL",
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