diff --git a/CHANGES.txt b/CHANGES.txt
index 72577b41..328ebdf1 100644
--- a/CHANGES.txt
+++ b/CHANGES.txt
@@ -1,6 +1,9 @@
-0.7dev
-======
+Release 0.7 21-Dec-2010
+-----------------------
 
+Full details about new features and changes can be found here:
+
+    http://www.myhdl.org/doc/0.7/whatsnew/0.7.html
 
 Release 0.6 9-Jan-2009
 -----------------------
diff --git a/README.txt b/README.txt
index b619d0f4..9ce83fe2 100644
--- a/README.txt
+++ b/README.txt
@@ -1,5 +1,5 @@
-MyHDL 0.7dev
-============
+MyHDL 0.7
+=========
 
 What is MyHDL?
 --------------
@@ -22,13 +22,13 @@ Documentation
 -------------
 The manual is available on-line:
 
-   http://www.myhdl.org/doc/0.6/manual
+   http://www.myhdl.org/doc/0.7/manual
 
 What's new
 ----------
 To find out what's new in this release, please read:
 
-    http://www.myhdl.org/doc/0.6/whatsnew/0.6.html
+    http://www.myhdl.org/doc/0.7/whatsnew/0.7.html
 
 Installation
 ------------
@@ -48,7 +48,8 @@ In this case, be sure to add the appropriate install dir to the
 $PYTHONPATH. 
 
 If necessary, consult the distutils documentation in the standard
-Python library if necessary for more details; or contact me.
+Python library if necessary for more details;
+or contact me.
 
 You can test the proper installation as follows:
    
diff --git a/doc/source/conf.py b/doc/source/conf.py
index eab994fd..7896d021 100644
--- a/doc/source/conf.py
+++ b/doc/source/conf.py
@@ -40,9 +40,9 @@ copyright = '2008-2010, Jan Decaluwe'
 # other places throughout the built documents.
 #
 # The short X.Y version.
-version = '0.7dev'
+version = '0.7'
 # The full version, including alpha/beta/rc tags.
-release = '0.7dev'
+release = '0.7'
 
 # There are two options for replacing |today|: either, you set today to some
 # non-false value, then it is used:
@@ -122,7 +122,8 @@ latex_font_size = '11pt'
 # Grouping the document tree into LaTeX files. List of tuples
 # (source start file, target name, title, author, document class [howto/manual]).
 latex_documents = [('manual/index', 'MyHDL.tex', 'MyHDL manual', 'Jan Decaluwe', 'manual'),
-                   ('whatsnew/0.6', 'whatsnew0.6.tex', 'What\'s new in MyHDL 0.6', 'Jan Decaluwe', 'manual')
+                   ('whatsnew/0.6', 'whatsnew0.6.tex', 'What\'s new in MyHDL 0.6', 'Jan Decaluwe', 'howto'),
+                   ('whatsnew/0.7', 'whatsnew0.7.tex', 'What\'s new in MyHDL 0.7', 'Jan Decaluwe', 'howto'),
                   ]
 
 # Additional stuff for the LaTeX preamble.
diff --git a/example/manual/FramerCtrl.v b/example/manual/FramerCtrl.v
index d4fd82be..b522710c 100644
--- a/example/manual/FramerCtrl.v
+++ b/example/manual/FramerCtrl.v
@@ -1,6 +1,6 @@
 // File: FramerCtrl.v
-// Generated by MyHDL 0.7dev
-// Date: Sun Oct 10 21:39:53 2010
+// Generated by MyHDL 0.7
+// Date: Sun Dec 19 16:52:33 2010
 
 
 `timescale 1ns/10ps
diff --git a/example/manual/FramerCtrl.vhd b/example/manual/FramerCtrl.vhd
index d06e021a..20e43140 100644
--- a/example/manual/FramerCtrl.vhd
+++ b/example/manual/FramerCtrl.vhd
@@ -1,6 +1,6 @@
 -- File: FramerCtrl.vhd
--- Generated by MyHDL 0.7dev
--- Date: Sun Oct 10 21:39:53 2010
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
 
 
 
@@ -20,7 +20,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_07dev.all;
+use work.pck_myhdl_07.all;
 
 use work.pck_FramerCtrl.all;
 
diff --git a/example/manual/GrayIncReg.v b/example/manual/GrayIncReg.v
index 4d4de8cc..2c115172 100644
--- a/example/manual/GrayIncReg.v
+++ b/example/manual/GrayIncReg.v
@@ -1,6 +1,6 @@
 // File: GrayIncReg.v
-// Generated by MyHDL 0.7dev
-// Date: Sun Oct 10 21:39:52 2010
+// Generated by MyHDL 0.7
+// Date: Sun Dec 19 16:52:33 2010
 
 
 `timescale 1ns/10ps
diff --git a/example/manual/GrayIncReg.vhd b/example/manual/GrayIncReg.vhd
index 9a1f9a15..d5c32712 100644
--- a/example/manual/GrayIncReg.vhd
+++ b/example/manual/GrayIncReg.vhd
@@ -1,6 +1,6 @@
 -- File: GrayIncReg.vhd
--- Generated by MyHDL 0.7dev
--- Date: Sun Oct 10 21:39:52 2010
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
 
 
 library IEEE;
@@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_07dev.all;
+use work.pck_myhdl_07.all;
 
 entity GrayIncReg is
     port (
diff --git a/example/manual/Inc.v b/example/manual/Inc.v
index 4b2faa23..c9bf8c68 100644
--- a/example/manual/Inc.v
+++ b/example/manual/Inc.v
@@ -1,6 +1,6 @@
 // File: Inc.v
-// Generated by MyHDL 0.7dev
-// Date: Sun Oct 10 21:39:52 2010
+// Generated by MyHDL 0.7
+// Date: Sun Dec 19 16:52:33 2010
 
 
 `timescale 1ns/10ps
diff --git a/example/manual/Inc.vhd b/example/manual/Inc.vhd
index 4140722f..02d8970e 100644
--- a/example/manual/Inc.vhd
+++ b/example/manual/Inc.vhd
@@ -1,6 +1,6 @@
 -- File: Inc.vhd
--- Generated by MyHDL 0.7dev
--- Date: Sun Oct 10 21:39:52 2010
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
 
 
 library IEEE;
@@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_07dev.all;
+use work.pck_myhdl_07.all;
 
 entity Inc is
     port (
diff --git a/example/manual/bin2gray.v b/example/manual/bin2gray.v
index 5266b74e..5fde5e30 100644
--- a/example/manual/bin2gray.v
+++ b/example/manual/bin2gray.v
@@ -1,6 +1,6 @@
 // File: bin2gray.v
-// Generated by MyHDL 0.7dev
-// Date: Sun Oct 10 21:39:52 2010
+// Generated by MyHDL 0.7
+// Date: Sun Dec 19 16:52:33 2010
 
 
 `timescale 1ns/10ps
diff --git a/example/manual/bin2gray.vhd b/example/manual/bin2gray.vhd
index 6857b4e8..948ab3cc 100644
--- a/example/manual/bin2gray.vhd
+++ b/example/manual/bin2gray.vhd
@@ -1,6 +1,6 @@
 -- File: bin2gray.vhd
--- Generated by MyHDL 0.7dev
--- Date: Sun Oct 10 21:39:52 2010
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
 
 
 library IEEE;
@@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_07dev.all;
+use work.pck_myhdl_07.all;
 
 entity bin2gray is
     port (
diff --git a/example/manual/inc_comb.v b/example/manual/inc_comb.v
index ffd00cad..2e71b539 100644
--- a/example/manual/inc_comb.v
+++ b/example/manual/inc_comb.v
@@ -1,6 +1,6 @@
 // File: inc_comb.v
-// Generated by MyHDL 0.7dev
-// Date: Fri Dec 17 11:39:33 2010
+// Generated by MyHDL 0.7
+// Date: Sun Dec 19 16:52:33 2010
 
 
 `timescale 1ns/10ps
diff --git a/example/manual/inc_comb.vhd b/example/manual/inc_comb.vhd
index c7b912ff..72473bfc 100644
--- a/example/manual/inc_comb.vhd
+++ b/example/manual/inc_comb.vhd
@@ -1,6 +1,6 @@
 -- File: inc_comb.vhd
--- Generated by MyHDL 0.7dev
--- Date: Fri Dec 17 11:39:33 2010
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
 
 
 library IEEE;
@@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_07dev.all;
+use work.pck_myhdl_07.all;
 
 entity inc_comb is
     port (
diff --git a/example/manual/pck_myhdl_07dev.vhd b/example/manual/pck_myhdl_07.vhd
similarity index 94%
rename from example/manual/pck_myhdl_07dev.vhd
rename to example/manual/pck_myhdl_07.vhd
index ff3a1736..65a85502 100644
--- a/example/manual/pck_myhdl_07dev.vhd
+++ b/example/manual/pck_myhdl_07.vhd
@@ -1,12 +1,13 @@
--- File: pck_myhdl_07dev.vhd
--- Generated by MyHDL 0.7dev
--- Date: Fri Jul  2 13:23:50 2010
+-- File: pck_myhdl_07.vhd
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
+
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-package pck_myhdl_07dev is
+package pck_myhdl_07 is
 
     attribute enum_encoding: string;
 
@@ -36,10 +37,10 @@ package pck_myhdl_07dev is
 
     function "-" (arg: unsigned) return signed;
 
-end pck_myhdl_07dev;
+end pck_myhdl_07;
 
 
-package body pck_myhdl_07dev is
+package body pck_myhdl_07 is
 
     function to_std_logic (arg: boolean) return std_logic is
     begin
@@ -135,6 +136,6 @@ package body pck_myhdl_07dev is
         return - signed(resize(arg, arg'length+1));
     end function "-";
 
-end pck_myhdl_07dev;
+end pck_myhdl_07;
 
 
diff --git a/example/manual/ram.vhd b/example/manual/ram.vhd
index c426e06c..14b4ea9e 100644
--- a/example/manual/ram.vhd
+++ b/example/manual/ram.vhd
@@ -1,6 +1,6 @@
 -- File: ram.vhd
--- Generated by MyHDL 0.7dev
--- Date: Sun Oct 10 21:39:53 2010
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
 
 
 library IEEE;
@@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_07dev.all;
+use work.pck_myhdl_07.all;
 
 entity ram is
     port (
diff --git a/example/manual/ram_1.v b/example/manual/ram_1.v
index c20de03d..b6af86be 100644
--- a/example/manual/ram_1.v
+++ b/example/manual/ram_1.v
@@ -1,6 +1,6 @@
 // File: ram_1.v
-// Generated by MyHDL 0.7dev
-// Date: Sun Oct 10 21:39:53 2010
+// Generated by MyHDL 0.7
+// Date: Sun Dec 19 16:52:33 2010
 
 
 `timescale 1ns/10ps
diff --git a/example/manual/rom.v b/example/manual/rom.v
index a36861ff..8d287240 100644
--- a/example/manual/rom.v
+++ b/example/manual/rom.v
@@ -1,6 +1,6 @@
 // File: rom.v
-// Generated by MyHDL 0.7dev
-// Date: Sun Oct 10 21:39:53 2010
+// Generated by MyHDL 0.7
+// Date: Sun Dec 19 16:52:33 2010
 
 
 `timescale 1ns/10ps
diff --git a/example/manual/rom.vhd b/example/manual/rom.vhd
index 5f4224fe..38cfc58d 100644
--- a/example/manual/rom.vhd
+++ b/example/manual/rom.vhd
@@ -1,6 +1,6 @@
 -- File: rom.vhd
--- Generated by MyHDL 0.7dev
--- Date: Sun Oct 10 21:39:53 2010
+-- Generated by MyHDL 0.7
+-- Date: Sun Dec 19 16:52:33 2010
 
 
 library IEEE;
@@ -8,7 +8,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_07dev.all;
+use work.pck_myhdl_07.all;
 
 entity rom is
     port (
diff --git a/myhdl/__init__.py b/myhdl/__init__.py
index 3cb7de70..9f405a18 100644
--- a/myhdl/__init__.py
+++ b/myhdl/__init__.py
@@ -46,7 +46,7 @@ toVerilog -- function that converts a design to Verilog
 
 """
 
-__version__ = "0.7dev"
+__version__ = "0.7"
 
 import sys
 import warnings
diff --git a/setup.py b/setup.py
index d0a017cb..110b8ccc 100644
--- a/setup.py
+++ b/setup.py
@@ -22,7 +22,7 @@ if sys.version_info < requiredVersion:
 from distutils.core import setup
 
 classifiers = """\
-Development Status :: 3 - Alpha
+Development Status :: 4 - Beta 
 Intended Audience :: Developers
 License :: OSI Approved :: GNU Library or Lesser General Public License (LGPL)
 Operating System :: OS Independent
@@ -32,12 +32,12 @@ Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
 
     
 setup(name="myhdl",
-      version="0.7dev",
+      version="0.7",
       description="Python as a Hardware Description Language",
       long_description = "See home page.",
       author="Jan Decaluwe",
       author_email="jan@jandecaluwe.com",
-      url="http://jandecaluwe.com/Tools/MyHDL/Overview.html",
+      url="http://www.myhdl.org",
       download_url="http://sourceforge.net/project/showfiles.php?group_id=91207",
       packages=['myhdl', 'myhdl.conversion'],
       license="LGPL",