FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

*** empty log message ***

Browse Source
This commit is contained in:
jand 2004-02-26 22:59:55 +00:00
parent 965b83d95a
commit 52c9a8f776
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
myhdl/_extractHierarchy.py
View File

@ -205,10 +205,10 @@ def _getGens(arg):
else:
l = []
for elt in arg:
if type(arg) is GeneratorType:
l.append(arg)
elif type(arg) is _AlwaysComb:
l.append(arg.gen)
if type(elt) is GeneratorType:
l.append(elt)
elif type(elt) is _AlwaysComb:
l.append(elt.gen)
return l