diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index 667ec080..7942963a 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -1865,7 +1865,7 @@ def _convertInitVal(reg, init):
         if abs(init) < 2 ** 31:
             v = '%sto_%s(%s, %s)%s' % (pre, vhd_tipe, init, len(reg), suf)
         else:
-            v = '%s%s\'"%s"%s' % (pre, vhd_tipe, tobin(init, len(reg)), suf)
+            v = '%s%s\'("%s")%s' % (pre, vhd_tipe, tobin(init, len(reg)), suf)
     else:
         assert isinstance(init, EnumItemType)
         v = init._toVHDL()
diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py
index a04a0bc0..b3b77066 100644
--- a/myhdl/conversion/_verify.py
+++ b/myhdl/conversion/_verify.py
@@ -43,7 +43,7 @@ registerSimulator(
     hdl="VHDL",
     analyze="ghdl -a --std=08 --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
     elaborate="ghdl -e --std=08 --workdir=work %(unitname)s",
-    simulate="ghdl -r --workdir=work %(unitname)s"
+    simulate="ghdl -r --std=08 --workdir=work %(unitname)s --ieee-asserts=disable"
 )
 
 registerSimulator(
@@ -137,9 +137,9 @@ class _VerificationClass(object):
 
         if isinstance(func, _Block):
             if hdl == "VHDL":
-                inst = func.convert(hdl='VHDL')
+                inst = func.convert(hdl='VHDL', **kwargs)
             else:
-                inst = func.convert(hdl='Verilog')
+                inst = func.convert(hdl='Verilog', **kwargs)
         else:
             if hdl == "VHDL":
                 inst = toVHDL(func, *args, **kwargs)
diff --git a/myhdl/test/conversion/general/test_initial_values.py b/myhdl/test/conversion/general/test_initial_values.py
index 053c06bf..2e867dec 100644
--- a/myhdl/test/conversion/general/test_initial_values.py
+++ b/myhdl/test/conversion/general/test_initial_values.py
@@ -547,6 +547,53 @@ def test_memory_convert():
         toVHDL.initial_values = pre_viv
 
 
+@block
+def init_reset_tb():
+
+    clk = Signal(bool(0))
+    reset = ResetSignal(0, active=1, isasync=False)
+
+    s_large = Signal(intbv(0xc0000000)[32:])
+    s_small = Signal(intbv(0xc)[32:])
+
+    @instance
+    def clkgen():
+
+        clk.next = 0
+        for n in range(10):
+            yield delay(10)
+            clk.next = not clk
+
+        raise StopSimulation()
+
+    @instance
+    def raise_reset():
+        yield clk.posedge
+        reset.next = 1
+        yield clk.posedge
+        reset.next = 0
+
+    @always_seq(clk.posedge,reset=reset)
+    def seq():
+
+        print(s_large)
+        print(s_small)
+        s_large.next = s_large + 1
+        s_small.next = s_small + 1
+
+    return instances()
+
+
+def test_init_reset():
+    """ Test assignment of initial values of signals used in an always_seq block with a reset signal
+        Because the _convertInitVal in _toVHDL.py does special handling depending on the init value
+        the test takes this into account.
+    """
+
+    inst = init_reset_tb()
+    assert conversion.verify(inst,initial_values=True) == 0
+
+
 #def test_init_used_list():
 #    '''It should be the _init attribute of each element in the list
 #    that is used for initialisation