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cleared out remaining debug-print

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This commit is contained in:
Josy Boelen 2021-03-08 09:55:28 +01:00
parent 65c456b680
commit 55e7113311
1 changed files with 0 additions and 5 deletions
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5
myhdl/conversion/_toVerilog.py
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@ -893,21 +893,17 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
def visit_Constant(self, node):
if node.value is None:
# NameConstant
print('NameConstant: None')
self.write(nameconstant_map[node.obj])
elif isinstance(node.value, bool):
print('NameConstant: bool')
self.write(nameconstant_map[node.obj])
elif isinstance(node.value, int):
# Num
print('Num')
if self.context == _context.PRINT:
self.write('"%s"' % node.value)
else:
self.write(self.IntRepr(node.value))
elif isinstance(node.value, str):
# Str
print('Str')
s = node.value
if self.context == _context.PRINT:
self.write('"%s"' % s)
@ -1204,7 +1200,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.writeline()
self.write("endcase")
else:
print (type(obj), type(a))
self.write('$write("%s", ' % fs)
self.visit(a)
self.write(');')