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next re-write

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This commit is contained in:
Josy Boelen 2021-03-06 20:34:11 +01:00
parent fddbd06595
commit 55e823e939
2 changed files with 107 additions and 31 deletions
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17
myhdl/conversion/_analyze.py
View File

@ -685,21 +685,20 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
if sys.version_info >= (3, 8, 0):
def visit_Constant(self, node):
node.obj = None # safeguarding?
# ToDo check for tuples?
if node.value in (True, False, None):
if isinstance(node.value, int):
# Num
if node.value in (0, 1):
node.obj = bool(node.value)
else:
node.obj = node.value
elif node.value in (True, False, None):
# NameConstant
node.obj = node.value
elif isinstance(node.value, str):
# Str
node.obj = node.value
else:
# Num?
if node.value in (0, 1):
node.obj = bool(node.value)
elif isinstance(node.value, int):
node.obj = node.value
else:
node.obj = None
else:

81
myhdl/test/conversion/general/test_loops.py
View File

@ -2,15 +2,16 @@ import os
path = os.path
from random import randrange
import myhdl
from myhdl import *
from myhdl.conversion import verify, analyze
from myhdl import ConversionError
from myhdl.conversion._misc import _error
@block
def ForLoopError1(a, out):
@instance
def logic():
while 1:
@ -20,10 +21,13 @@ def ForLoopError1(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoopError2(a, out):
@instance
def logic():
while 1:
@ -33,10 +37,13 @@ def ForLoopError2(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop1(a, out):
@instance
def logic():
while 1:
@ -46,10 +53,13 @@ def ForLoop1(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop2(a, out):
@instance
def logic():
while 1:
@ -59,10 +69,13 @@ def ForLoop2(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop3(a, out):
@instance
def logic():
while 1:
@ -72,10 +85,13 @@ def ForLoop3(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop4(a, out):
@instance
def logic():
while 1:
@ -85,10 +101,13 @@ def ForLoop4(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop5(a, out):
@instance
def logic():
while 1:
@ -98,10 +117,13 @@ def ForLoop5(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop6(a, out):
@instance
def logic():
while 1:
@ -111,10 +133,13 @@ def ForLoop6(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForContinueLoop(a, out):
@instance
def logic():
while 1:
@ -125,10 +150,13 @@ def ForContinueLoop(a, out):
continue
var += 1
out.next = var
return logic
@block
def ForBreakLoop(a, out):
@instance
def logic():
while 1:
@ -138,10 +166,13 @@ def ForBreakLoop(a, out):
if a[i] == 1:
out.next = i
break
return logic
@block
def ForBreakContinueLoop(a, out):
@instance
def logic():
while 1:
@ -152,10 +183,13 @@ def ForBreakContinueLoop(a, out):
continue
out.next = i
break
return logic
@block
def NestedForLoop1(a, out):
@instance
def logic():
while 1:
@ -170,10 +204,13 @@ def NestedForLoop1(a, out):
var += 1
break
out.next = var
return logic
@block
def NestedForLoop2(a, out):
@instance
def logic():
while 1:
@ -191,23 +228,29 @@ def NestedForLoop2(a, out):
out.next = j
break
break
return logic
def ReturnFromFunction(a):
for i in downrange(len(a)):
if a[i] == 1:
return i
return 0
@block
def FunctionCall(a, out):
@instance
def logic():
while 1:
yield a
out.next = ReturnFromFunction(a)
return logic
# During the following check, I noticed that non-blocking assignments
# are not scheduled when a task is disabled in Icarus. Apparently
# this is one of the many vague areas in the Verilog standard.
@ -218,8 +261,10 @@ def ReturnFromTask(a, out):
return
out[:] = 23 # to notice it
@block
def TaskCall(a, out):
@instance
def logic():
var = intbv(0)[8:]
@ -227,10 +272,13 @@ def TaskCall(a, out):
yield a
ReturnFromTask(a, var)
out.next = var
return logic
@block
def WhileLoop(a, out):
@instance
def logic():
while 1:
@ -242,10 +290,13 @@ def WhileLoop(a, out):
var += 1
i -= 1
out.next = var
return logic
@block
def WhileContinueLoop(a, out):
@instance
def logic():
while 1:
@ -259,10 +310,13 @@ def WhileContinueLoop(a, out):
var += 1
i -= 1
out.next = var
return logic
@block
def WhileBreakLoop(a, out):
@instance
def logic():
while 1:
@ -275,10 +329,13 @@ def WhileBreakLoop(a, out):
out.next = i
break
i -= 1
return logic
@block
def WhileBreakContinueLoop(a, out):
@instance
def logic():
while 1:
@ -292,8 +349,10 @@ def WhileBreakContinueLoop(a, out):
continue
out.next = i
break
return logic
@block
def LoopBench(LoopTest):
@ -321,6 +380,7 @@ def testForLoopError1():
else:
assert False
def testForLoopError2():
try:
analyze(LoopBench(ForLoopError2))
@ -329,47 +389,64 @@ def testForLoopError2():
else:
assert False
def testForLoop1():
assert verify(LoopBench(ForLoop1)) == 0
def testForLoop2():
assert verify(LoopBench(ForLoop2)) == 0
def testForLoop4():
assert verify(LoopBench(ForLoop4)) == 0
def testForLoop5():
assert verify(LoopBench(ForLoop5)) == 0
# for loop 3 and 6 can't work in vhdl
def testForContinueLoop():
assert verify(LoopBench(ForContinueLoop)) == 0
def testForBreakLoop():
assert verify(LoopBench(ForBreakLoop)) == 0
def testForBreakContinueLoop():
assert verify(LoopBench(ForBreakContinueLoop)) == 0
def testNestedForLoop1():
assert verify(LoopBench(NestedForLoop1)) == 0
def testNestedForLoop2():
assert verify(LoopBench(NestedForLoop2)) == 0
def testWhileLoop():
def testFunctionCall():
assert verify(LoopBench(FunctionCall)) == 0
# # def testTaskCall(self):
# # sim = self.bench(TaskCall)
# # Simulation(sim).run()
def testWhileLoop():
assert verify(LoopBench(WhileLoop)) == 0
def testWhileContinueLoop():
assert verify(LoopBench(WhileContinueLoop)) == 0
def testWhileBreakLoop():
assert verify(LoopBench(WhileBreakLoop)) == 0
def testWhileBreakContinueLoop():
assert verify(LoopBench(WhileBreakContinueLoop)) == 0