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ConcatSignal
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@ -23,13 +23,19 @@
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"""
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from myhdl._Signal import _Signal
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from myhdl._Waiter import _SignalWaiter, _SignalTupleWaiter
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from myhdl._intbv import intbv
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# shadow signals
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class _ShadowSignal(_Signal):
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__slots__ = ('gen', )
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__slots__ = ('gen', 'waiter')
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def __init__(self, val):
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_Signal.__init__(self, val)
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self.driven = True
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@ -40,9 +46,9 @@ class _SliceSignal(_ShadowSignal):
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def __init__(self, sig, left, right=None):
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### XXX error checks
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if right is None:
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_Signal.__init__(self, sig[left])
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_ShadowSignal.__init__(self, sig[left])
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else:
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_Signal.__init__(self, sig[left:right])
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_ShadowSignal.__init__(self, sig[left:right])
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self.sig = sig
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self.left = left
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self.right = right
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@ -50,7 +56,7 @@ class _SliceSignal(_ShadowSignal):
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self.gen = self.genfuncIndex()
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else:
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self.gen = self.genfuncSlice()
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self._driven = True
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self.waiter = _SignalWaiter(self.gen)
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def genfuncIndex(self):
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sig, index = self.sig, self.left
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@ -77,3 +83,42 @@ class _SliceSignal(_ShadowSignal):
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return "%s <= %s(%s);" % (self._name, self.sig._name, self.left)
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else:
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return "%s <= %s(%s-1 downto %s);" % (self._name, self.sig._name, self.left, self.right)
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class ConcatSignal(_ShadowSignal):
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__slots__ = ('_args',)
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def __init__(self, *args):
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assert len(args) >= 2
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self._args = args
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### XXX error checks
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nrbits = 0
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for a in args:
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nrbits += len(a)
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ini = intbv(0)[nrbits:]
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hi = nrbits
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for a in args:
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lo = hi - len(a)
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ini[hi:lo] = a
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hi = lo
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_ShadowSignal.__init__(self, ini)
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self.gen = self.genfunc()
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self.waiter = _SignalTupleWaiter(self.gen)
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def genfunc(self):
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set_next = _Signal._set_next
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args = self._args
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nrbits = self._nrbits
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newval = intbv(0)[nrbits:]
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while 1:
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hi = nrbits
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for a in args:
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lo = hi - len(a)
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newval[hi:lo] = a
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hi = lo
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set_next(self, newval)
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yield args
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@ -224,10 +224,9 @@ def _makeWaiters(arglist):
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raise SimulationError(_error.DuplicatedArg)
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ids.add(id(arg))
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# add waiters for shadow signals
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# waiter wrapping done here to avoid circular imports
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for sig in _signals:
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if not isinstance(sig, _ShadowSignal):
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continue
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waiters.append(_SignalWaiter(sig.gen))
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waiters.append(sig.waiter)
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return waiters, cosim
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@ -24,6 +24,7 @@ Simulation -- simulation class
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StopStimulation -- exception that stops a simulation
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now -- function that returns the current time
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Signal -- class to model hardware signals
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ConcatSignal -- class that models a concatenation shadow signal
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delay -- callable to model delay in a yield statement
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posedge -- callable to model a rising edge on a signal in a yield statement
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negedge -- callable to model a falling edge on a signal in a yield statement
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@ -36,7 +37,6 @@ bin -- returns a binary string representation.
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concat -- function to concat ints, bitstrings, bools, intbvs, Signals
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-- returns an intbv
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instances -- function that returns all instances defined in a function
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processes -- function that returns all processes defined in a function
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always_comb -- function that returns an input-sensitive generator
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enum -- function that returns an enumeration type
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traceSignals -- function that enables signal tracing in a VCD file
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@ -110,6 +110,7 @@ from _concat import concat
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from _intbv import intbv
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from _join import join
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from _Signal import posedge, negedge, Signal
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from _ShadowSignal import ConcatSignal
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from _simulator import now
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from _delay import delay
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from _Cosimulation import Cosimulation
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@ -135,6 +136,7 @@ __all__ = ["bin",
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"posedge",
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"negedge",
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"Signal",
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"ConcatSignal",
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"now",
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"delay",
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"downrange",
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@ -1,6 +1,6 @@
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from myhdl import *
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def bench_ShadowSignal():
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def bench_SliceSignal():
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s = Signal(intbv(0)[8:])
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a, b, c = s(7), s(5), s(0)
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@ -22,6 +22,41 @@ def bench_ShadowSignal():
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return check
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def test_ShadowSignal():
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Simulation(bench_ShadowSignal()).run()
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def test_SliceSignal():
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Simulation(bench_SliceSignal()).run()
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def bench_ConcatSignal():
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a = Signal(intbv(0)[8:])
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b = Signal(bool(0))
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c = Signal(intbv(0)[3:])
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d = Signal(intbv(0)[4:])
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s = ConcatSignal(a, b, c, d)
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@instance
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def check():
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for i in range(2**len(a)):
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for j in (0, 1):
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for k in range(len(c)):
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for m in range(len(d)):
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a.next = i
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b.next = j
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c.next = k
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d.next = m
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yield delay(10)
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assert s[16:8] == a
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assert s[7] == b
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assert s[7:4] == c
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assert s[4:] == d
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return check
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def test_ConcatSignal():
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Simulation(bench_ConcatSignal()).run()
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