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Merge branch 'jck-py3-conv'

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This commit is contained in:
Jan Decaluwe 2015-03-18 20:17:12 +01:00
commit 5934e06383
24 changed files with 169 additions and 120 deletions
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3
myhdl/_enum.py
View File

@ -77,6 +77,9 @@ def enum(*names, **kwargs):
self._nritems = type._nritems
self._type = type
def __hash__(self):
return hash((self._type, self._index))
def __repr__(self):
return self._name

35
myhdl/conversion/_analyze.py
View File

@ -20,7 +20,7 @@
""" MyHDL conversion analysis module.
"""
from __future__ import absolute_import
from __future__ import absolute_import, print_function
import inspect
# import compiler
@ -39,13 +39,14 @@ from myhdl._always_comb import _AlwaysComb
from myhdl._always_seq import _AlwaysSeq
from myhdl._always import _Always
from myhdl.conversion._misc import (_error, _access, _kind,
_ConversionMixin, _Label, _genUniqueSuffix)
_ConversionMixin, _Label, _genUniqueSuffix,
_get_argnames)
from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode
from myhdl._Signal import _Signal, _WaiterList
from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal, _TristateDriver
from myhdl._util import _isTupleOfInts, _dedent, _flatten, _makeAST
from myhdl._resolverefs import _AttrRefTransformer
from myhdl._compat import builtins, integer_types
from myhdl._compat import builtins, integer_types, PY2
myhdlObjects = myhdl.__dict__.values()
builtinObjects = builtins.__dict__.values()
@ -287,7 +288,7 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
if not self.toplevel:
self.raiseError(node, _error.NotSupported, "embedded function definition")
self.toplevel = False
node.argnames = [arg.id for arg in node.args.args]
node.argnames = _get_argnames(node)
# don't visit decorator lists - they can support more than other calls
# put official docstrings aside for separate processing
node.doc = None
@ -559,6 +560,13 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
def visit_Call(self, node):
self.visit(node.func)
f = self.getObj(node.func)
node.obj = None
if f is print:
self.visit_Print(node)
return
self.access = _access.UNKNOWN
for arg in node.args:
self.visit(arg)
@ -566,8 +574,6 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
self.visit(kw)
self.access = _access.INPUT
argsAreInputs = True
f = self.getObj(node.func)
node.obj = None
if type(f) is type and issubclass(f, intbv):
node.obj = self.getVal(node)
elif f is concat:
@ -614,7 +620,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
v.visit(tree)
node.obj = tree.returnObj
node.tree = tree
tree.argnames = argnames = [arg.id for arg in tree.body[0].args.args]
tree.argnames = argnames = _get_argnames(tree.body[0])
# extend argument list with keyword arguments on the correct position
node.args.extend([None]*len(node.keywords))
for kw in node.keywords:
@ -766,6 +772,9 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
self.raiseError(node, _error.UnsupportedListComp)
mem.depth = cf.args[0].obj
def visit_NameConstant(self, node):
node.obj = node.value
def visit_Name(self, node):
if isinstance(node.ctx, ast.Store):
self.setName(node)
@ -893,7 +902,13 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
f = []
nr = 0
a = []
for n in node.values:
if PY2 and isinstance(node, ast.Print):
node_args = node.values
else:
node_args = node.args
for n in node_args:
if isinstance(n, ast.BinOp) and isinstance(n.op, ast.Mod) and \
isinstance(n.left, ast.Str):
if isinstance(n.right, ast.Tuple):
@ -1169,7 +1184,7 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
def visit_FunctionDef(self, node):
self.refStack.push()
argnames = [arg.id for arg in node.args.args]
argnames = _get_argnames(node)
for i, arg in enumerate(self.args):
n = argnames[i]
self.tree.symdict[n] = self.getObj(arg)
@ -1276,7 +1291,7 @@ class _AnalyzeTopFuncVisitor(_AnalyzeVisitor):
def visit_FunctionDef(self, node):
self.name = node.name
self.argnames = [arg.id for arg in node.args.args]
self.argnames = _get_argnames(node)
if isboundmethod(self.func):
if not self.argnames[0] == 'self':
self.raiseError(node, _error.NotSupported,

7
myhdl/conversion/_misc.py
View File

@ -30,6 +30,7 @@ import myhdl
from myhdl import *
from myhdl import ConversionError
from myhdl._util import _flatten
from myhdl._compat import PY2
class _error(object):
FirstArgType = "first argument should be a classic function"
@ -209,3 +210,9 @@ class _namesVisitor(ast.NodeVisitor):
def visit_Name(self, node):
self.names.append(node.id)
def _get_argnames(node):
if PY2:
return [arg.id for arg in node.args.args]
else:
return [arg.arg for arg in node.args.args]

19
myhdl/conversion/_toVHDL.py
View File

@ -275,7 +275,7 @@ def _writeCustomPackage(f, intf):
print("attribute enum_encoding: string;", file=f)
print(file=f)
sortedList = list(_enumPortTypeSet)
sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name))
sortedList.sort(key=lambda x: x._name)
for t in sortedList:
print(" %s" % t._toVHDL(), file=f)
print(file=f)
@ -366,7 +366,7 @@ def _writeConstants(f):
def _writeTypeDefs(f):
f.write("\n")
sortedList = list(_enumTypeSet)
sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name))
sortedList.sort(key=lambda x: x._name)
for t in sortedList:
f.write("%s\n" % t._toVHDL())
f.write("\n")
@ -926,6 +926,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
fn = node.func
# assert isinstance(fn, astNode.Name)
f = self.getObj(fn)
if f is print:
self.visit_Print(node)
return
fname = ''
pre, suf = '', ''
opening, closing = '(', ')'
@ -1243,6 +1248,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
for stmt in node.body:
self.visit(stmt)
def visit_NameConstant(self, node):
node.id = str(node.value)
self.getName(node)
def visit_Name(self, node):
if isinstance(node.ctx, ast.Store):
self.setName(node)
@ -1975,7 +1984,7 @@ def inferVhdlObj(obj):
if (isinstance(obj, _Signal) and obj._type is intbv) or \
isinstance(obj, intbv):
ls = getattr(obj, 'lenStr', False)
if obj.min < 0:
if obj.min is None or obj.min < 0:
vhd = vhd_signed(size=len(obj), lenStr=ls)
else:
vhd = vhd_unsigned(size=len(obj), lenStr=ls)
@ -2101,6 +2110,10 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
self.tree.vardict[var] = _loopInt(-1)
self.generic_visit(node)
def visit_NameConstant(self, node):
node.vhd = inferVhdlObj(node.value)
node.vhdOri = copy(node.vhd)
def visit_Name(self, node):
if node.id in self.tree.vardict:
node.obj = self.tree.vardict[node.id]

32
myhdl/conversion/_toVerilog.py
View File

@ -39,7 +39,7 @@ import warnings
import myhdl
from myhdl import *
from myhdl._compat import integer_types, class_types
from myhdl._compat import integer_types, class_types, PY2
from myhdl import ToVerilogError, ToVerilogWarning
from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo,
_UserVerilogCode, _userCodeMap)
@ -175,7 +175,7 @@ class _ToVerilogConvertor(object):
# build portmap for cosimulation
portmap = {}
for n, s in intf.argdict.iteritems():
for n, s in intf.argdict.items():
if hasattr(s, 'driver'): portmap[n] = s.driver()
else: portmap[n] = s
self.portmap = portmap
@ -443,6 +443,12 @@ opmap = {
ast.Or : '||',
}
nameconstant_map = {
True: "1'b1",
False: "0'b1",
None: "'bz"
}
class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
@ -716,6 +722,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
fn = node.func
# assert isinstance(fn, astNode.Name)
f = self.getObj(fn)
if f is print:
self.visit_Print(node)
return
opening, closing = '(', ')'
if f is bool:
self.write("(")
@ -982,6 +993,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
def visit_ListComp(self, node):
pass # do nothing
def visit_NameConstant(self, node):
self.write(nameconstant_map[node.obj])
def visit_Name(self, node):
if isinstance(node.ctx, ast.Store):
self.setName(node)
@ -992,16 +1006,14 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.write(node.id)
def getName(self, node):
n = node.id
if PY2 and n in ('True', 'False', 'None'):
self.visit_NameConstant(node)
return
addSignBit = False
isMixedExpr = (not node.signed) and (self.context == _context.SIGNED)
n = node.id
if n == 'False':
s = "1'b0"
elif n == 'True':
s = "1'b1"
elif n == 'None':
s = "'bz"
elif n in self.tree.vardict:
if n in self.tree.vardict:
addSignBit = isMixedExpr
s = n
elif n in self.tree.argnames:

4
myhdl/conversion/_verify.py
View File

@ -152,7 +152,7 @@ class _VerificationClass(object):
print("Analysis succeeded", file=sys.stderr)
return 0
f = tempfile.TemporaryFile()
f = tempfile.TemporaryFile(mode='w+t')
sys.stdout = f
sim = Simulation(inst)
sim.run()
@ -174,7 +174,7 @@ class _VerificationClass(object):
print("Elaboration failed", file=sys.stderr)
return ret
g = tempfile.TemporaryFile()
g = tempfile.TemporaryFile(mode='w+t')
#print(simulate)
ret = subprocess.call(simulate, stdout=g, shell=True)
# if ret != 0:

24
myhdl/test/conversion/general/test_ShadowSignal.py
View File

@ -13,13 +13,13 @@ def bench_SliceSignal():
for i in range(N):
s.next = i
yield delay(10)
print int(a)
print int(b)
print int(c)
print d
print e
print f
print g
print(int(a))
print(int(b))
print(int(c))
print(d)
print(e)
print(f)
print(g)
return check
@ -52,7 +52,7 @@ def bench_ConcatSignal():
c.next = k
d.next = m
yield delay(10)
print s
print(s)
return check
@ -78,15 +78,15 @@ def bench_TristateSignal():
#print s
a.next = 1
yield delay(10)
print s
print(s)
a.next = None
b.next = 122
yield delay(10)
print s
print(s)
b.next = None
c.next = 233
yield delay(10)
print s
print(s)
c.next = None
yield delay(10)
#print s
@ -129,7 +129,7 @@ def bench_permute(conv=False):
for i in range(2**len(a)):
a.next = i
yield delay(10)
print x, a
print("%d %d" % (x, a))
assert x[2] == a[0]
assert x[1] == a[2]
assert x[0] == a[1]

2
myhdl/test/conversion/general/test_adapter.py
View File

@ -56,7 +56,7 @@ def bench_adapter(conv=False):
assert o_err[1] == (i_err[2] | i_err[3] | i_err[4] | i_err[5])
assert o_err[2] == i_err[1]
assert o_err[3] == i_err[0]
print o_err
print(o_err)
return dut, stimulus

2
myhdl/test/conversion/general/test_bin2gray.py
View File

@ -60,7 +60,7 @@ def bin2grayBench(width, bin2gray):
#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
#print bin(G, width)
#print bin(G_v, width)
print "%d" % G
print("%d" % G)
return stimulus, bin2gray_inst

2
myhdl/test/conversion/general/test_case.py
View File

@ -70,7 +70,7 @@ def bench_case(map_case, N):
for i in range(N):
a.next = i
yield delay(10)
print z
print(z)
return stimulus, inst

4
myhdl/test/conversion/general/test_dec.py
View File

@ -166,11 +166,11 @@ def DecBench(dec):
def check():
yield reset.negedge
yield reset.posedge
print count
print(count)
while 1:
yield clock.posedge
yield delay(1)
print count
print(count)
dec_inst = dec(count, enable, clock, reset, n=n)

2
myhdl/test/conversion/general/test_fsm.py
View File

@ -102,7 +102,7 @@ def FSMBench(FramerCtrl, t_State):
yield clk.posedge
while True:
yield clk.negedge
print "negedge"
print("negedge")
# in the end, this should work
# print state

8
myhdl/test/conversion/general/test_hec.py
View File

@ -117,9 +117,9 @@ def HecCalculator_v(name, hec, header):
headers = [ 0x00000000L,
0x01234567L,
0xbac6f4caL
headers = [ 0x00000000,
0x01234567,
0xbac6f4ca
]
headers.extend([randrange(2**32-1) for i in range(10)])
@ -139,7 +139,7 @@ def HecBench(HecCalculator):
for i in range(len(headers)):
header.next = headers[i]
yield delay(10)
print hec
print(hec)
return stimulus, heccalc_inst

2
myhdl/test/conversion/general/test_inc.py
View File

@ -157,7 +157,7 @@ def IncBench(inc):
yield clock.negedge
while True:
yield clock.negedge
print count
print(count)
return inc_inst, clockgen, monitor

6
myhdl/test/conversion/general/test_intbv_signed.py
View File

@ -51,7 +51,7 @@ def PlainIntbv():
@instance
def logic():
print "Plain Instance Test"
print("Plain Instance Test")
yield delay(10)
# intbv with positive range, pos number, and msb not set, return signed()
@ -208,7 +208,7 @@ def SlicedSigned():
def logic():
b = intbv(4, min=-8, max=8)
a = intbv(4, min=-8, max=8)
print "SLicedSigned test"
print("SLicedSigned test")
yield delay(10)
b[:] = a[4:]
assert b == 4
@ -228,7 +228,7 @@ def SignedConcat():
@instance
def logic():
print "Signed Concat test"
print("Signed Concat test")
yield delay(10)
# concat 3 bits

10
myhdl/test/conversion/general/test_listofsigs.py
View File

@ -32,7 +32,7 @@ def intbv2list():
a.next = i
yield delay(10)
assert z == a
print a
print(a)
raise StopSimulation
return extract, assemble, stimulus
@ -186,7 +186,7 @@ def processlist(case, inv):
a.next = i
yield delay(10)
assert z == ~a
print z
print(z)
raise StopSimulation
return case_inst, stimulus
@ -225,7 +225,7 @@ def unsigned():
a[0].next = 2
a[1].next = 5
yield delay(10)
print z
print(z)
return logic, stimulus
@ -247,7 +247,7 @@ def signed():
a[0].next = 2
a[1].next = -5
yield delay(10)
print z
print(z)
return logic, stimulus
@ -270,7 +270,7 @@ def mixed():
a[0].next = -6
b[2].next = 15
yield delay(10)
print z
print(z)
return logic, stimulus

2
myhdl/test/conversion/general/test_loops.py
View File

@ -291,7 +291,7 @@ def LoopBench(LoopTest):
for i in range(100):
a.next = data[i]
yield delay(10)
print z
print(z)
return stimulus, looptest_inst

2
myhdl/test/conversion/general/test_method.py
View File

@ -136,7 +136,7 @@ def ObjBench(hObj):
x.next = nx
yield clk.posedge
yield clk.posedge
print "x %d y %d" % (x, y)
print("x %d y %d" % (x, y))
assert x == nx
assert y == ny
raise StopSimulation

8
myhdl/test/conversion/general/test_nonlocal.py
View File

@ -40,19 +40,19 @@ def NonlocalBench():
yield clk.negedge
reset.next = 1
yield clk.negedge
print qout
print(qout)
assert qout == ONE
reset.next = 0
for i in range(100):
yield clk.negedge
print qout
print(qout)
init.next = 1
yield clk.negedge
assert qout == ALL_ONES
print qout
print(qout)
init.next = 0
for i in range(300):
print qout
print(qout)
raise StopSimulation()
return scrambler, clkgen, stimulus

51
myhdl/test/conversion/general/test_numass.py
View File

@ -15,40 +15,39 @@ def NumassBench():
@instance
def check():
p.next = 0
q.next = 0
r.next = 0
s.next = 0
p.next = 0
q.next = 0
r.next = 0
s.next = 0
yield delay(10)
print p, q, r ,s
p.next = 1
q.next = 1
r.next = 1
s.next = 1
print("%d %d %d %d" % (p, q, r, s))
p.next = 1
q.next = 1
r.next = 1
s.next = 1
yield delay(10)
print p, q, r ,s
p.next = 2
q.next = 2
r.next = -2
s.next = -2
print("%d %d %d %d" % (p, q, r, s))
p.next = 2
q.next = 2
r.next = -2
s.next = -2
yield delay(10)
print p, q, r ,s
p.next = 255
q.next = 246836311517
r.next = 255
s.next = -246836311517
print("%d %d %d %d" % (p, q, r, s))
p.next = 255
q.next = 246836311517
r.next = 255
s.next = -246836311517
yield delay(10)
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
p.next = 254
q.next = PBIGINT
r.next = -256
s.next = NBIGINT
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0]))
p.next = 254
q.next = PBIGINT
r.next = -256
s.next = NBIGINT
yield delay(10)
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0]))
return check
def test_numass():
assert conversion.verify(NumassBench) == 0

58
myhdl/test/conversion/general/test_print.py
View File

@ -21,47 +21,47 @@ def PrintBench():
i2[:] = -7
si2.next = -5
yield delay(10)
print
print i1
print i2
print i1, i2
print si1
print si2
print('')
print(i1)
print(i2)
print("%d %d" % (i1, i2))
print(si1)
print(si2)
yield delay(10)
print "This is a test"
print("This is a test")
yield delay(10)
print int(b)
print int(sb)
print(int(b))
print(int(sb))
yield delay(10)
print "i1 is %s" % i1
print("i1 is %s" % i1)
yield delay(10)
print "i1 is %s, i2 is %s" % (i1, i2)
print "i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2)
print "i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2)
print b
print("i1 is %s, i2 is %s" % (i1, i2))
print("i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2))
print("i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2))
print(b)
#print "%% %s" % i1
yield delay(10)
print state
print "the state is %s" % state
print "the state is %s" % (state,)
print "i1 is %s and the state is %s" % (i1, state)
print(state)
print("the state is %s" % state)
print("the state is %s" % (state,))
print("i1 is %s and the state is %s" % (i1, state))
# ord test
yield delay(10)
print ord('y')
print ord('2')
print(ord('y'))
print(ord('2'))
# signed
yield delay(10)
print i1.signed()
print i2.signed()
print si1.signed()
print si2.signed()
print(i1.signed())
print(i2.signed())
print(si1.signed())
print(si2.signed())
return logic
@ -76,7 +76,7 @@ def PrintError1():
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print "floating point %f end" % i1
print("floating point %f end" % i1)
return logic
def testPrintError1():
@ -92,7 +92,7 @@ def PrintError2():
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print "begin %s %s end" % i1
print("begin %s %s end" % i1)
return logic
def testPrintError2():
@ -109,7 +109,7 @@ def PrintError3():
i1 = intbv(12)[8:]
i2 = intbv(13)[8:]
yield delay(10)
print "begin %s end" % (i1, i2)
print("begin %s end" % (i1, i2))
return logic
def testPrintError3():
@ -125,7 +125,7 @@ def PrintError4():
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print "%10s" % i1
print("%10s" % i1)
return logic
def testPrintError4():
@ -141,7 +141,7 @@ def PrintError5():
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print "%-10s" % i1
print("%-10s" % i1)
return logic
def testPrintError5():

2
myhdl/test/conversion/general/test_ram.py
View File

@ -117,7 +117,7 @@ def RamBench(ram, depth=128):
yield clk.posedge
yield delay(1)
assert dout == i
print dout
print(dout)
raise StopSimulation()
@instance

2
myhdl/test/conversion/general/test_rom.py
View File

@ -73,7 +73,7 @@ def RomBench(rom):
yield delay(1)
if __debug__:
assert dout == ROM[i]
print dout
print(dout)
raise StopSimulation()
@instance

2
myhdl/test/conversion/general/test_ternary.py
View File

@ -55,7 +55,7 @@ def TernaryBench(ternary):
clk.next = 1
yield delay(10)
assert dout == (i + 1) % 128
print dout
print(dout)
clk.next = 0
yield delay(10)