From 9cb4b23ef9b0b7b8798cff12ca6b1af317530a2f Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Fri, 6 Feb 2015 07:01:30 -0500 Subject: [PATCH 01/12] handle py3's renaming of argument names in the ast In python3, arg is a raw string of the argument name. In python2, arguments are represented as Name nodes. The _get_argnames function is introduced for accessing argument names in a version agnostic way. --- myhdl/conversion/_analyze.py | 11 ++++++----- myhdl/conversion/_misc.py | 7 +++++++ 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index dfa4328e..6dea2259 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -39,7 +39,8 @@ from myhdl._always_comb import _AlwaysComb from myhdl._always_seq import _AlwaysSeq from myhdl._always import _Always from myhdl.conversion._misc import (_error, _access, _kind, - _ConversionMixin, _Label, _genUniqueSuffix) + _ConversionMixin, _Label, _genUniqueSuffix, + _get_argnames) from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode from myhdl._Signal import _Signal, _WaiterList from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal, _TristateDriver @@ -287,7 +288,7 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin): if not self.toplevel: self.raiseError(node, _error.NotSupported, "embedded function definition") self.toplevel = False - node.argnames = [arg.id for arg in node.args.args] + node.argnames = _get_argnames(node) # don't visit decorator lists - they can support more than other calls # put official docstrings aside for separate processing node.doc = None @@ -614,7 +615,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): v.visit(tree) node.obj = tree.returnObj node.tree = tree - tree.argnames = argnames = [arg.id for arg in tree.body[0].args.args] + tree.argnames = argnames = _get_argnames(tree.body[0]) # extend argument list with keyword arguments on the correct position node.args.extend([None]*len(node.keywords)) for kw in node.keywords: @@ -1169,7 +1170,7 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor): def visit_FunctionDef(self, node): self.refStack.push() - argnames = [arg.id for arg in node.args.args] + argnames = _get_argnames(node) for i, arg in enumerate(self.args): n = argnames[i] self.tree.symdict[n] = self.getObj(arg) @@ -1276,7 +1277,7 @@ class _AnalyzeTopFuncVisitor(_AnalyzeVisitor): def visit_FunctionDef(self, node): self.name = node.name - self.argnames = [arg.id for arg in node.args.args] + self.argnames = _get_argnames(node) if isboundmethod(self.func): if not self.argnames[0] == 'self': self.raiseError(node, _error.NotSupported, diff --git a/myhdl/conversion/_misc.py b/myhdl/conversion/_misc.py index 4e1def35..3129cd73 100644 --- a/myhdl/conversion/_misc.py +++ b/myhdl/conversion/_misc.py @@ -30,6 +30,7 @@ import myhdl from myhdl import * from myhdl import ConversionError from myhdl._util import _flatten +from myhdl._compat import PY2 class _error(object): FirstArgType = "first argument should be a classic function" @@ -209,3 +210,9 @@ class _namesVisitor(ast.NodeVisitor): def visit_Name(self, node): self.names.append(node.id) + +def _get_argnames(node): + if PY2: + return [arg.id for arg in node.args.args] + else: + return [arg.arg for arg in node.args.args] From 2cb885283ca490ce85de621805bd6efecaabee87 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Tue, 17 Mar 2015 17:21:08 -0400 Subject: [PATCH 02/12] replace iteritems with items in toverilog --- myhdl/conversion/_toVerilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 15a41105..d3a60d19 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -175,7 +175,7 @@ class _ToVerilogConvertor(object): # build portmap for cosimulation portmap = {} - for n, s in intf.argdict.iteritems(): + for n, s in intf.argdict.items(): if hasattr(s, 'driver'): portmap[n] = s.driver() else: portmap[n] = s self.portmap = portmap From 7f500d1ec0d9821b4092512348a9512304822c86 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Tue, 17 Mar 2015 17:44:55 -0400 Subject: [PATCH 03/12] Add parentheses to print statements in most general conv tests NOTE: This is equavalent to using a print statement on a tuple in py2. In py3, it is a print function. --- myhdl/test/conversion/general/test_adapter.py | 2 +- myhdl/test/conversion/general/test_bin2gray.py | 2 +- myhdl/test/conversion/general/test_case.py | 2 +- myhdl/test/conversion/general/test_dec.py | 4 ++-- myhdl/test/conversion/general/test_fsm.py | 2 +- myhdl/test/conversion/general/test_hec.py | 2 +- myhdl/test/conversion/general/test_inc.py | 2 +- myhdl/test/conversion/general/test_intbv_signed.py | 6 +++--- myhdl/test/conversion/general/test_listofsigs.py | 10 +++++----- myhdl/test/conversion/general/test_loops.py | 2 +- myhdl/test/conversion/general/test_method.py | 2 +- myhdl/test/conversion/general/test_nonlocal.py | 8 ++++---- myhdl/test/conversion/general/test_ram.py | 2 +- myhdl/test/conversion/general/test_rom.py | 2 +- myhdl/test/conversion/general/test_ternary.py | 2 +- 15 files changed, 25 insertions(+), 25 deletions(-) diff --git a/myhdl/test/conversion/general/test_adapter.py b/myhdl/test/conversion/general/test_adapter.py index 89f01599..118b2403 100644 --- a/myhdl/test/conversion/general/test_adapter.py +++ b/myhdl/test/conversion/general/test_adapter.py @@ -56,7 +56,7 @@ def bench_adapter(conv=False): assert o_err[1] == (i_err[2] | i_err[3] | i_err[4] | i_err[5]) assert o_err[2] == i_err[1] assert o_err[3] == i_err[0] - print o_err + print(o_err) return dut, stimulus diff --git a/myhdl/test/conversion/general/test_bin2gray.py b/myhdl/test/conversion/general/test_bin2gray.py index 66ec04ed..f1745c41 100644 --- a/myhdl/test/conversion/general/test_bin2gray.py +++ b/myhdl/test/conversion/general/test_bin2gray.py @@ -60,7 +60,7 @@ def bin2grayBench(width, bin2gray): #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width) #print bin(G, width) #print bin(G_v, width) - print "%d" % G + print("%d" % G) return stimulus, bin2gray_inst diff --git a/myhdl/test/conversion/general/test_case.py b/myhdl/test/conversion/general/test_case.py index 99f17628..239bd704 100644 --- a/myhdl/test/conversion/general/test_case.py +++ b/myhdl/test/conversion/general/test_case.py @@ -70,7 +70,7 @@ def bench_case(map_case, N): for i in range(N): a.next = i yield delay(10) - print z + print(z) return stimulus, inst diff --git a/myhdl/test/conversion/general/test_dec.py b/myhdl/test/conversion/general/test_dec.py index 10965f09..efc32d0f 100644 --- a/myhdl/test/conversion/general/test_dec.py +++ b/myhdl/test/conversion/general/test_dec.py @@ -166,11 +166,11 @@ def DecBench(dec): def check(): yield reset.negedge yield reset.posedge - print count + print(count) while 1: yield clock.posedge yield delay(1) - print count + print(count) dec_inst = dec(count, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/general/test_fsm.py b/myhdl/test/conversion/general/test_fsm.py index 35d6f36c..a1408e71 100644 --- a/myhdl/test/conversion/general/test_fsm.py +++ b/myhdl/test/conversion/general/test_fsm.py @@ -102,7 +102,7 @@ def FSMBench(FramerCtrl, t_State): yield clk.posedge while True: yield clk.negedge - print "negedge" + print("negedge") # in the end, this should work # print state diff --git a/myhdl/test/conversion/general/test_hec.py b/myhdl/test/conversion/general/test_hec.py index 95623608..c386edce 100644 --- a/myhdl/test/conversion/general/test_hec.py +++ b/myhdl/test/conversion/general/test_hec.py @@ -139,7 +139,7 @@ def HecBench(HecCalculator): for i in range(len(headers)): header.next = headers[i] yield delay(10) - print hec + print(hec) return stimulus, heccalc_inst diff --git a/myhdl/test/conversion/general/test_inc.py b/myhdl/test/conversion/general/test_inc.py index 69782e29..c9ccd560 100644 --- a/myhdl/test/conversion/general/test_inc.py +++ b/myhdl/test/conversion/general/test_inc.py @@ -157,7 +157,7 @@ def IncBench(inc): yield clock.negedge while True: yield clock.negedge - print count + print(count) return inc_inst, clockgen, monitor diff --git a/myhdl/test/conversion/general/test_intbv_signed.py b/myhdl/test/conversion/general/test_intbv_signed.py index 562d1e27..8f478b81 100644 --- a/myhdl/test/conversion/general/test_intbv_signed.py +++ b/myhdl/test/conversion/general/test_intbv_signed.py @@ -51,7 +51,7 @@ def PlainIntbv(): @instance def logic(): - print "Plain Instance Test" + print("Plain Instance Test") yield delay(10) # intbv with positive range, pos number, and msb not set, return signed() @@ -208,7 +208,7 @@ def SlicedSigned(): def logic(): b = intbv(4, min=-8, max=8) a = intbv(4, min=-8, max=8) - print "SLicedSigned test" + print("SLicedSigned test") yield delay(10) b[:] = a[4:] assert b == 4 @@ -228,7 +228,7 @@ def SignedConcat(): @instance def logic(): - print "Signed Concat test" + print("Signed Concat test") yield delay(10) # concat 3 bits diff --git a/myhdl/test/conversion/general/test_listofsigs.py b/myhdl/test/conversion/general/test_listofsigs.py index 31a12624..6d706b9f 100644 --- a/myhdl/test/conversion/general/test_listofsigs.py +++ b/myhdl/test/conversion/general/test_listofsigs.py @@ -32,7 +32,7 @@ def intbv2list(): a.next = i yield delay(10) assert z == a - print a + print(a) raise StopSimulation return extract, assemble, stimulus @@ -186,7 +186,7 @@ def processlist(case, inv): a.next = i yield delay(10) assert z == ~a - print z + print(z) raise StopSimulation return case_inst, stimulus @@ -225,7 +225,7 @@ def unsigned(): a[0].next = 2 a[1].next = 5 yield delay(10) - print z + print(z) return logic, stimulus @@ -247,7 +247,7 @@ def signed(): a[0].next = 2 a[1].next = -5 yield delay(10) - print z + print(z) return logic, stimulus @@ -270,7 +270,7 @@ def mixed(): a[0].next = -6 b[2].next = 15 yield delay(10) - print z + print(z) return logic, stimulus diff --git a/myhdl/test/conversion/general/test_loops.py b/myhdl/test/conversion/general/test_loops.py index 531f06bd..cd3b99a3 100644 --- a/myhdl/test/conversion/general/test_loops.py +++ b/myhdl/test/conversion/general/test_loops.py @@ -291,7 +291,7 @@ def LoopBench(LoopTest): for i in range(100): a.next = data[i] yield delay(10) - print z + print(z) return stimulus, looptest_inst diff --git a/myhdl/test/conversion/general/test_method.py b/myhdl/test/conversion/general/test_method.py index d3176025..bf7a5257 100644 --- a/myhdl/test/conversion/general/test_method.py +++ b/myhdl/test/conversion/general/test_method.py @@ -136,7 +136,7 @@ def ObjBench(hObj): x.next = nx yield clk.posedge yield clk.posedge - print "x %d y %d" % (x, y) + print("x %d y %d" % (x, y)) assert x == nx assert y == ny raise StopSimulation diff --git a/myhdl/test/conversion/general/test_nonlocal.py b/myhdl/test/conversion/general/test_nonlocal.py index 7a625e1c..ad72722e 100644 --- a/myhdl/test/conversion/general/test_nonlocal.py +++ b/myhdl/test/conversion/general/test_nonlocal.py @@ -40,19 +40,19 @@ def NonlocalBench(): yield clk.negedge reset.next = 1 yield clk.negedge - print qout + print(qout) assert qout == ONE reset.next = 0 for i in range(100): yield clk.negedge - print qout + print(qout) init.next = 1 yield clk.negedge assert qout == ALL_ONES - print qout + print(qout) init.next = 0 for i in range(300): - print qout + print(qout) raise StopSimulation() return scrambler, clkgen, stimulus diff --git a/myhdl/test/conversion/general/test_ram.py b/myhdl/test/conversion/general/test_ram.py index 3d51c2e5..4685dc47 100644 --- a/myhdl/test/conversion/general/test_ram.py +++ b/myhdl/test/conversion/general/test_ram.py @@ -117,7 +117,7 @@ def RamBench(ram, depth=128): yield clk.posedge yield delay(1) assert dout == i - print dout + print(dout) raise StopSimulation() @instance diff --git a/myhdl/test/conversion/general/test_rom.py b/myhdl/test/conversion/general/test_rom.py index 326b1959..fc1c9e23 100644 --- a/myhdl/test/conversion/general/test_rom.py +++ b/myhdl/test/conversion/general/test_rom.py @@ -73,7 +73,7 @@ def RomBench(rom): yield delay(1) if __debug__: assert dout == ROM[i] - print dout + print(dout) raise StopSimulation() @instance diff --git a/myhdl/test/conversion/general/test_ternary.py b/myhdl/test/conversion/general/test_ternary.py index 9871817e..c8e865f8 100644 --- a/myhdl/test/conversion/general/test_ternary.py +++ b/myhdl/test/conversion/general/test_ternary.py @@ -55,7 +55,7 @@ def TernaryBench(ternary): clk.next = 1 yield delay(10) assert dout == (i + 1) % 128 - print dout + print(dout) clk.next = 0 yield delay(10) From efce0a3e4f4ff19395628154940a49efef066a66 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Tue, 17 Mar 2015 18:03:42 -0400 Subject: [PATCH 04/12] use key instead of cmp while sorting list the cmp kwarg of list.sort method is deprecated in py3 --- myhdl/conversion/_toVHDL.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index a1552d76..5b2e7890 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -275,7 +275,7 @@ def _writeCustomPackage(f, intf): print("attribute enum_encoding: string;", file=f) print(file=f) sortedList = list(_enumPortTypeSet) - sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name)) + sortedList.sort(key=lambda x: x._name) for t in sortedList: print(" %s" % t._toVHDL(), file=f) print(file=f) @@ -366,7 +366,7 @@ def _writeConstants(f): def _writeTypeDefs(f): f.write("\n") sortedList = list(_enumTypeSet) - sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name)) + sortedList.sort(key=lambda x: x._name) for t in sortedList: f.write("%s\n" % t._toVHDL()) f.write("\n") From 2672e9a4c6ba934bcd6264e7b1c6262ff30d0406 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Tue, 17 Mar 2015 18:45:07 -0400 Subject: [PATCH 05/12] verify: create tmpfiles in text mode --- myhdl/conversion/_verify.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py index 36f9713b..4ed45c99 100644 --- a/myhdl/conversion/_verify.py +++ b/myhdl/conversion/_verify.py @@ -152,7 +152,7 @@ class _VerificationClass(object): print("Analysis succeeded", file=sys.stderr) return 0 - f = tempfile.TemporaryFile() + f = tempfile.TemporaryFile(mode='w+t') sys.stdout = f sim = Simulation(inst) sim.run() @@ -174,7 +174,7 @@ class _VerificationClass(object): print("Elaboration failed", file=sys.stderr) return ret - g = tempfile.TemporaryFile() + g = tempfile.TemporaryFile(mode='w+t') #print(simulate) ret = subprocess.call(simulate, stdout=g, shell=True) # if ret != 0: From 302c78fc3076c496e1d89da4384088050eff23d4 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Tue, 17 Mar 2015 18:48:43 -0400 Subject: [PATCH 06/12] support converting print functions --- myhdl/conversion/_analyze.py | 21 ++++++++++++++++----- myhdl/conversion/_toVHDL.py | 5 +++++ myhdl/conversion/_toVerilog.py | 5 +++++ 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index 6dea2259..c9b85729 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -20,7 +20,7 @@ """ MyHDL conversion analysis module. """ -from __future__ import absolute_import +from __future__ import absolute_import, print_function import inspect # import compiler @@ -46,7 +46,7 @@ from myhdl._Signal import _Signal, _WaiterList from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal, _TristateDriver from myhdl._util import _isTupleOfInts, _dedent, _flatten, _makeAST from myhdl._resolverefs import _AttrRefTransformer -from myhdl._compat import builtins, integer_types +from myhdl._compat import builtins, integer_types, PY2 myhdlObjects = myhdl.__dict__.values() builtinObjects = builtins.__dict__.values() @@ -560,6 +560,13 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): def visit_Call(self, node): self.visit(node.func) + f = self.getObj(node.func) + node.obj = None + + if f is print: + self.visit_Print(node) + return + self.access = _access.UNKNOWN for arg in node.args: self.visit(arg) @@ -567,8 +574,6 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): self.visit(kw) self.access = _access.INPUT argsAreInputs = True - f = self.getObj(node.func) - node.obj = None if type(f) is type and issubclass(f, intbv): node.obj = self.getVal(node) elif f is concat: @@ -894,7 +899,13 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): f = [] nr = 0 a = [] - for n in node.values: + + if PY2 and isinstance(node, ast.Print): + node_args = node.values + else: + node_args = node.args + + for n in node_args: if isinstance(n, ast.BinOp) and isinstance(n.op, ast.Mod) and \ isinstance(n.left, ast.Str): if isinstance(n.right, ast.Tuple): diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 5b2e7890..8fea8d33 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -926,6 +926,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): fn = node.func # assert isinstance(fn, astNode.Name) f = self.getObj(fn) + + if f is print: + self.visit_Print(node) + return + fname = '' pre, suf = '', '' opening, closing = '(', ')' diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index d3a60d19..6d6f431a 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -716,6 +716,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): fn = node.func # assert isinstance(fn, astNode.Name) f = self.getObj(fn) + + if f is print: + self.visit_Print(node) + return + opening, closing = '(', ')' if f is bool: self.write("(") From 608a233ba032f4eecb5582819c635659416d51ad Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Tue, 17 Mar 2015 19:47:25 -0400 Subject: [PATCH 07/12] handle nameconstants In py2, True False and None are instances of ast.Name with ctx=load. However, in py3.4, they are instances of ast.NameConstant and the value attribute holds one of these constants. --- myhdl/conversion/_analyze.py | 3 +++ myhdl/conversion/_toVHDL.py | 8 ++++++++ myhdl/conversion/_toVerilog.py | 25 ++++++++++++++++--------- 3 files changed, 27 insertions(+), 9 deletions(-) diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index c9b85729..63399168 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -772,6 +772,9 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): self.raiseError(node, _error.UnsupportedListComp) mem.depth = cf.args[0].obj + def visit_NameConstant(self, node): + node.obj = node.value + def visit_Name(self, node): if isinstance(node.ctx, ast.Store): self.setName(node) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 8fea8d33..de34546f 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -1248,6 +1248,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): for stmt in node.body: self.visit(stmt) + def visit_NameConstant(self, node): + node.id = str(node.value) + self.getName(node) + def visit_Name(self, node): if isinstance(node.ctx, ast.Store): self.setName(node) @@ -2106,6 +2110,10 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin): self.tree.vardict[var] = _loopInt(-1) self.generic_visit(node) + def visit_NameConstant(self, node): + node.vhd = inferVhdlObj(node.value) + node.vhdOri = copy(node.vhd) + def visit_Name(self, node): if node.id in self.tree.vardict: node.obj = self.tree.vardict[node.id] diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 6d6f431a..3643019b 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -39,7 +39,7 @@ import warnings import myhdl from myhdl import * -from myhdl._compat import integer_types, class_types +from myhdl._compat import integer_types, class_types, PY2 from myhdl import ToVerilogError, ToVerilogWarning from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo, _UserVerilogCode, _userCodeMap) @@ -443,6 +443,12 @@ opmap = { ast.Or : '||', } +nameconstant_map = { + True: "1'b1", + False: "0'b1", + None: "'bz" +} + class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): @@ -987,6 +993,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): def visit_ListComp(self, node): pass # do nothing + def visit_NameConstant(self, node): + self.write(nameconstant_map[node.obj]) + def visit_Name(self, node): if isinstance(node.ctx, ast.Store): self.setName(node) @@ -997,16 +1006,14 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): self.write(node.id) def getName(self, node): + n = node.id + if PY2 and n in ('True', 'False', 'None'): + self.visit_NameConstant(node) + return + addSignBit = False isMixedExpr = (not node.signed) and (self.context == _context.SIGNED) - n = node.id - if n == 'False': - s = "1'b0" - elif n == 'True': - s = "1'b1" - elif n == 'None': - s = "'bz" - elif n in self.tree.vardict: + if n in self.tree.vardict: addSignBit = isMixedExpr s = n elif n in self.tree.argnames: From cafe06382d816c6e0874320b92b4619ea8f544ef Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Wed, 18 Mar 2015 01:07:06 -0400 Subject: [PATCH 08/12] fix long literals in test_hec --- myhdl/test/conversion/general/test_hec.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/myhdl/test/conversion/general/test_hec.py b/myhdl/test/conversion/general/test_hec.py index c386edce..d8816a57 100644 --- a/myhdl/test/conversion/general/test_hec.py +++ b/myhdl/test/conversion/general/test_hec.py @@ -117,9 +117,9 @@ def HecCalculator_v(name, hec, header): -headers = [ 0x00000000L, - 0x01234567L, - 0xbac6f4caL +headers = [ 0x00000000, + 0x01234567, + 0xbac6f4ca ] headers.extend([randrange(2**32-1) for i in range(10)]) From 287065284458b2af5655b3680615359fe6ae7ec6 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Wed, 18 Mar 2015 04:47:58 -0400 Subject: [PATCH 09/12] Implement __hash__ for EnumItem In python 3, if a class defines __eq__, the inheritance of __hash__ is blocked. Therefore, __hash__ needs to be defined explicitly. For EnumItem, we use self._type and self._index since they are sufficent for uniquely identifying any particular EnumItem. --- myhdl/_enum.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/myhdl/_enum.py b/myhdl/_enum.py index aac32fc3..81293f5b 100644 --- a/myhdl/_enum.py +++ b/myhdl/_enum.py @@ -77,6 +77,9 @@ def enum(*names, **kwargs): self._nritems = type._nritems self._type = type + def __hash__(self): + return hash((self._type, self._index)) + def __repr__(self): return self._name From bb1fdfe904bffaf37641bf438945b1b7bb21c4fe Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Wed, 18 Mar 2015 05:08:10 -0400 Subject: [PATCH 10/12] fix inferVhdlObj behaviour when obj.min is None In python 2, None < 0 returns True However, in py3, None cannot be compared with zero. This commit ensures identical behaviour in py2,3 when obj.min is None --- myhdl/conversion/_toVHDL.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index de34546f..ef5528d3 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -1984,7 +1984,7 @@ def inferVhdlObj(obj): if (isinstance(obj, _Signal) and obj._type is intbv) or \ isinstance(obj, intbv): ls = getattr(obj, 'lenStr', False) - if obj.min < 0: + if obj.min is None or obj.min < 0: vhd = vhd_signed(size=len(obj), lenStr=ls) else: vhd = vhd_unsigned(size=len(obj), lenStr=ls) From 1be1f77f641be132fd6d086c58e3f741db0b8374 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Wed, 18 Mar 2015 05:20:19 -0400 Subject: [PATCH 11/12] use parantheses in print statements of remaining general conv tests --- .../conversion/general/test_ShadowSignal.py | 24 ++++---- myhdl/test/conversion/general/test_numass.py | 10 ++-- myhdl/test/conversion/general/test_print.py | 58 +++++++++---------- 3 files changed, 46 insertions(+), 46 deletions(-) diff --git a/myhdl/test/conversion/general/test_ShadowSignal.py b/myhdl/test/conversion/general/test_ShadowSignal.py index 50b1ebd9..35cae418 100644 --- a/myhdl/test/conversion/general/test_ShadowSignal.py +++ b/myhdl/test/conversion/general/test_ShadowSignal.py @@ -13,13 +13,13 @@ def bench_SliceSignal(): for i in range(N): s.next = i yield delay(10) - print int(a) - print int(b) - print int(c) - print d - print e - print f - print g + print(int(a)) + print(int(b)) + print(int(c)) + print(d) + print(e) + print(f) + print(g) return check @@ -52,7 +52,7 @@ def bench_ConcatSignal(): c.next = k d.next = m yield delay(10) - print s + print(s) return check @@ -78,15 +78,15 @@ def bench_TristateSignal(): #print s a.next = 1 yield delay(10) - print s + print(s) a.next = None b.next = 122 yield delay(10) - print s + print(s) b.next = None c.next = 233 yield delay(10) - print s + print(s) c.next = None yield delay(10) #print s @@ -129,7 +129,7 @@ def bench_permute(conv=False): for i in range(2**len(a)): a.next = i yield delay(10) - print x, a + print(x, a) assert x[2] == a[0] assert x[1] == a[2] assert x[0] == a[1] diff --git a/myhdl/test/conversion/general/test_numass.py b/myhdl/test/conversion/general/test_numass.py index d8420834..10a5b736 100644 --- a/myhdl/test/conversion/general/test_numass.py +++ b/myhdl/test/conversion/general/test_numass.py @@ -20,31 +20,31 @@ def NumassBench(): r.next = 0 s.next = 0 yield delay(10) - print p, q, r ,s + print(p, q, r ,s) p.next = 1 q.next = 1 r.next = 1 s.next = 1 yield delay(10) - print p, q, r ,s + print(p, q, r ,s) p.next = 2 q.next = 2 r.next = -2 s.next = -2 yield delay(10) - print p, q, r ,s + print(p, q, r ,s) p.next = 255 q.next = 246836311517 r.next = 255 s.next = -246836311517 yield delay(10) - print p, q[40:20], q[20:0], r ,s[41:20], s[20:0] + print(p, q[40:20], q[20:0], r ,s[41:20], s[20:0]) p.next = 254 q.next = PBIGINT r.next = -256 s.next = NBIGINT yield delay(10) - print p, q[40:20], q[20:0], r ,s[41:20], s[20:0] + print(p, q[40:20], q[20:0], r ,s[41:20], s[20:0]) return check diff --git a/myhdl/test/conversion/general/test_print.py b/myhdl/test/conversion/general/test_print.py index aacce37a..af802031 100644 --- a/myhdl/test/conversion/general/test_print.py +++ b/myhdl/test/conversion/general/test_print.py @@ -21,47 +21,47 @@ def PrintBench(): i2[:] = -7 si2.next = -5 yield delay(10) - print - print i1 - print i2 - print i1, i2 - print si1 - print si2 + print() + print(i1) + print(i2) + print(i1, i2) + print(si1) + print(si2) yield delay(10) - print "This is a test" + print("This is a test") yield delay(10) - print int(b) - print int(sb) + print(int(b)) + print(int(sb)) yield delay(10) - print "i1 is %s" % i1 + print("i1 is %s" % i1) yield delay(10) - print "i1 is %s, i2 is %s" % (i1, i2) - print "i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2) - print "i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2) - print b + print("i1 is %s, i2 is %s" % (i1, i2)) + print("i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2)) + print("i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2)) + print(b) #print "%% %s" % i1 yield delay(10) - print state - print "the state is %s" % state - print "the state is %s" % (state,) - print "i1 is %s and the state is %s" % (i1, state) + print(state) + print("the state is %s" % state) + print("the state is %s" % (state,)) + print("i1 is %s and the state is %s" % (i1, state)) # ord test yield delay(10) - print ord('y') - print ord('2') + print(ord('y')) + print(ord('2')) # signed yield delay(10) - print i1.signed() - print i2.signed() - print si1.signed() - print si2.signed() + print(i1.signed()) + print(i2.signed()) + print(si1.signed()) + print(si2.signed()) return logic @@ -76,7 +76,7 @@ def PrintError1(): def logic(): i1 = intbv(12)[8:] yield delay(10) - print "floating point %f end" % i1 + print("floating point %f end" % i1) return logic def testPrintError1(): @@ -92,7 +92,7 @@ def PrintError2(): def logic(): i1 = intbv(12)[8:] yield delay(10) - print "begin %s %s end" % i1 + print("begin %s %s end" % i1) return logic def testPrintError2(): @@ -109,7 +109,7 @@ def PrintError3(): i1 = intbv(12)[8:] i2 = intbv(13)[8:] yield delay(10) - print "begin %s end" % (i1, i2) + print("begin %s end" % (i1, i2)) return logic def testPrintError3(): @@ -125,7 +125,7 @@ def PrintError4(): def logic(): i1 = intbv(12)[8:] yield delay(10) - print "%10s" % i1 + print("%10s" % i1) return logic def testPrintError4(): @@ -141,7 +141,7 @@ def PrintError5(): def logic(): i1 = intbv(12)[8:] yield delay(10) - print "%-10s" % i1 + print("%-10s" % i1) return logic def testPrintError5(): From 43b5f18e6795939f2070cede1c8adb784b3be028 Mon Sep 17 00:00:00 2001 From: Keerthan Jaic Date: Wed, 18 Mar 2015 05:26:53 -0400 Subject: [PATCH 12/12] fix tests which fail on python2 because they try to print a tuple --- .../conversion/general/test_ShadowSignal.py | 2 +- myhdl/test/conversion/general/test_numass.py | 51 +++++++++---------- myhdl/test/conversion/general/test_print.py | 4 +- 3 files changed, 28 insertions(+), 29 deletions(-) diff --git a/myhdl/test/conversion/general/test_ShadowSignal.py b/myhdl/test/conversion/general/test_ShadowSignal.py index 35cae418..4b3ace65 100644 --- a/myhdl/test/conversion/general/test_ShadowSignal.py +++ b/myhdl/test/conversion/general/test_ShadowSignal.py @@ -129,7 +129,7 @@ def bench_permute(conv=False): for i in range(2**len(a)): a.next = i yield delay(10) - print(x, a) + print("%d %d" % (x, a)) assert x[2] == a[0] assert x[1] == a[2] assert x[0] == a[1] diff --git a/myhdl/test/conversion/general/test_numass.py b/myhdl/test/conversion/general/test_numass.py index 10a5b736..c5e1b291 100644 --- a/myhdl/test/conversion/general/test_numass.py +++ b/myhdl/test/conversion/general/test_numass.py @@ -15,40 +15,39 @@ def NumassBench(): @instance def check(): - p.next = 0 - q.next = 0 - r.next = 0 - s.next = 0 + p.next = 0 + q.next = 0 + r.next = 0 + s.next = 0 yield delay(10) - print(p, q, r ,s) - p.next = 1 - q.next = 1 - r.next = 1 - s.next = 1 + print("%d %d %d %d" % (p, q, r, s)) + p.next = 1 + q.next = 1 + r.next = 1 + s.next = 1 yield delay(10) - print(p, q, r ,s) - p.next = 2 - q.next = 2 - r.next = -2 - s.next = -2 + print("%d %d %d %d" % (p, q, r, s)) + p.next = 2 + q.next = 2 + r.next = -2 + s.next = -2 yield delay(10) - print(p, q, r ,s) - p.next = 255 - q.next = 246836311517 - r.next = 255 - s.next = -246836311517 + print("%d %d %d %d" % (p, q, r, s)) + p.next = 255 + q.next = 246836311517 + r.next = 255 + s.next = -246836311517 yield delay(10) - print(p, q[40:20], q[20:0], r ,s[41:20], s[20:0]) - p.next = 254 - q.next = PBIGINT - r.next = -256 - s.next = NBIGINT + print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0])) + p.next = 254 + q.next = PBIGINT + r.next = -256 + s.next = NBIGINT yield delay(10) - print(p, q[40:20], q[20:0], r ,s[41:20], s[20:0]) + print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0])) return check def test_numass(): assert conversion.verify(NumassBench) == 0 - diff --git a/myhdl/test/conversion/general/test_print.py b/myhdl/test/conversion/general/test_print.py index af802031..65ef9111 100644 --- a/myhdl/test/conversion/general/test_print.py +++ b/myhdl/test/conversion/general/test_print.py @@ -21,10 +21,10 @@ def PrintBench(): i2[:] = -7 si2.next = -5 yield delay(10) - print() + print('') print(i1) print(i2) - print(i1, i2) + print("%d %d" % (i1, i2)) print(si1) print(si2)