mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
Merge branch 'jck-py3-conv'
This commit is contained in:
commit
5934e06383
@ -77,6 +77,9 @@ def enum(*names, **kwargs):
|
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self._nritems = type._nritems
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self._nritems = type._nritems
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self._type = type
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self._type = type
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|
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|
def __hash__(self):
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|
return hash((self._type, self._index))
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|
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def __repr__(self):
|
def __repr__(self):
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return self._name
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return self._name
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|
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|
@ -20,7 +20,7 @@
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""" MyHDL conversion analysis module.
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""" MyHDL conversion analysis module.
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|
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"""
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"""
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from __future__ import absolute_import
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from __future__ import absolute_import, print_function
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|
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import inspect
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import inspect
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# import compiler
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# import compiler
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@ -39,13 +39,14 @@ from myhdl._always_comb import _AlwaysComb
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from myhdl._always_seq import _AlwaysSeq
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from myhdl._always_seq import _AlwaysSeq
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from myhdl._always import _Always
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from myhdl._always import _Always
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from myhdl.conversion._misc import (_error, _access, _kind,
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from myhdl.conversion._misc import (_error, _access, _kind,
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_ConversionMixin, _Label, _genUniqueSuffix)
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_ConversionMixin, _Label, _genUniqueSuffix,
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|
_get_argnames)
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from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode
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from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode
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from myhdl._Signal import _Signal, _WaiterList
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from myhdl._Signal import _Signal, _WaiterList
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from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal, _TristateDriver
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from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal, _TristateDriver
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from myhdl._util import _isTupleOfInts, _dedent, _flatten, _makeAST
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from myhdl._util import _isTupleOfInts, _dedent, _flatten, _makeAST
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from myhdl._resolverefs import _AttrRefTransformer
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from myhdl._resolverefs import _AttrRefTransformer
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from myhdl._compat import builtins, integer_types
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from myhdl._compat import builtins, integer_types, PY2
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|
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myhdlObjects = myhdl.__dict__.values()
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myhdlObjects = myhdl.__dict__.values()
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builtinObjects = builtins.__dict__.values()
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builtinObjects = builtins.__dict__.values()
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@ -287,7 +288,7 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
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if not self.toplevel:
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if not self.toplevel:
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = False
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self.toplevel = False
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node.argnames = [arg.id for arg in node.args.args]
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node.argnames = _get_argnames(node)
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# don't visit decorator lists - they can support more than other calls
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# don't visit decorator lists - they can support more than other calls
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# put official docstrings aside for separate processing
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# put official docstrings aside for separate processing
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node.doc = None
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node.doc = None
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@ -559,6 +560,13 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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|
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def visit_Call(self, node):
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def visit_Call(self, node):
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self.visit(node.func)
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self.visit(node.func)
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|
f = self.getObj(node.func)
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|
node.obj = None
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if f is print:
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self.visit_Print(node)
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|
return
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|
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self.access = _access.UNKNOWN
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self.access = _access.UNKNOWN
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for arg in node.args:
|
for arg in node.args:
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self.visit(arg)
|
self.visit(arg)
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@ -566,8 +574,6 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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self.visit(kw)
|
self.visit(kw)
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self.access = _access.INPUT
|
self.access = _access.INPUT
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argsAreInputs = True
|
argsAreInputs = True
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f = self.getObj(node.func)
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node.obj = None
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if type(f) is type and issubclass(f, intbv):
|
if type(f) is type and issubclass(f, intbv):
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node.obj = self.getVal(node)
|
node.obj = self.getVal(node)
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elif f is concat:
|
elif f is concat:
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@ -614,7 +620,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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v.visit(tree)
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v.visit(tree)
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node.obj = tree.returnObj
|
node.obj = tree.returnObj
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node.tree = tree
|
node.tree = tree
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tree.argnames = argnames = [arg.id for arg in tree.body[0].args.args]
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tree.argnames = argnames = _get_argnames(tree.body[0])
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# extend argument list with keyword arguments on the correct position
|
# extend argument list with keyword arguments on the correct position
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node.args.extend([None]*len(node.keywords))
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node.args.extend([None]*len(node.keywords))
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for kw in node.keywords:
|
for kw in node.keywords:
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@ -766,6 +772,9 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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self.raiseError(node, _error.UnsupportedListComp)
|
self.raiseError(node, _error.UnsupportedListComp)
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mem.depth = cf.args[0].obj
|
mem.depth = cf.args[0].obj
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|
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|
def visit_NameConstant(self, node):
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|
node.obj = node.value
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|
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def visit_Name(self, node):
|
def visit_Name(self, node):
|
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if isinstance(node.ctx, ast.Store):
|
if isinstance(node.ctx, ast.Store):
|
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self.setName(node)
|
self.setName(node)
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@ -893,7 +902,13 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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f = []
|
f = []
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nr = 0
|
nr = 0
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a = []
|
a = []
|
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for n in node.values:
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|
if PY2 and isinstance(node, ast.Print):
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|
node_args = node.values
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|
else:
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|
node_args = node.args
|
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|
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|
for n in node_args:
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if isinstance(n, ast.BinOp) and isinstance(n.op, ast.Mod) and \
|
if isinstance(n, ast.BinOp) and isinstance(n.op, ast.Mod) and \
|
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isinstance(n.left, ast.Str):
|
isinstance(n.left, ast.Str):
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if isinstance(n.right, ast.Tuple):
|
if isinstance(n.right, ast.Tuple):
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@ -1169,7 +1184,7 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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def visit_FunctionDef(self, node):
|
def visit_FunctionDef(self, node):
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self.refStack.push()
|
self.refStack.push()
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argnames = [arg.id for arg in node.args.args]
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argnames = _get_argnames(node)
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for i, arg in enumerate(self.args):
|
for i, arg in enumerate(self.args):
|
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n = argnames[i]
|
n = argnames[i]
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self.tree.symdict[n] = self.getObj(arg)
|
self.tree.symdict[n] = self.getObj(arg)
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@ -1276,7 +1291,7 @@ class _AnalyzeTopFuncVisitor(_AnalyzeVisitor):
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def visit_FunctionDef(self, node):
|
def visit_FunctionDef(self, node):
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|
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self.name = node.name
|
self.name = node.name
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self.argnames = [arg.id for arg in node.args.args]
|
self.argnames = _get_argnames(node)
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if isboundmethod(self.func):
|
if isboundmethod(self.func):
|
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if not self.argnames[0] == 'self':
|
if not self.argnames[0] == 'self':
|
||||||
self.raiseError(node, _error.NotSupported,
|
self.raiseError(node, _error.NotSupported,
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|
@ -30,6 +30,7 @@ import myhdl
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from myhdl import *
|
from myhdl import *
|
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from myhdl import ConversionError
|
from myhdl import ConversionError
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from myhdl._util import _flatten
|
from myhdl._util import _flatten
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|
from myhdl._compat import PY2
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|
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class _error(object):
|
class _error(object):
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FirstArgType = "first argument should be a classic function"
|
FirstArgType = "first argument should be a classic function"
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@ -209,3 +210,9 @@ class _namesVisitor(ast.NodeVisitor):
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|
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def visit_Name(self, node):
|
def visit_Name(self, node):
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self.names.append(node.id)
|
self.names.append(node.id)
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|
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|
def _get_argnames(node):
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|
if PY2:
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|
return [arg.id for arg in node.args.args]
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|
else:
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|
return [arg.arg for arg in node.args.args]
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|
@ -275,7 +275,7 @@ def _writeCustomPackage(f, intf):
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print("attribute enum_encoding: string;", file=f)
|
print("attribute enum_encoding: string;", file=f)
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print(file=f)
|
print(file=f)
|
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sortedList = list(_enumPortTypeSet)
|
sortedList = list(_enumPortTypeSet)
|
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sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name))
|
sortedList.sort(key=lambda x: x._name)
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for t in sortedList:
|
for t in sortedList:
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print(" %s" % t._toVHDL(), file=f)
|
print(" %s" % t._toVHDL(), file=f)
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print(file=f)
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print(file=f)
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@ -366,7 +366,7 @@ def _writeConstants(f):
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def _writeTypeDefs(f):
|
def _writeTypeDefs(f):
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f.write("\n")
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f.write("\n")
|
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sortedList = list(_enumTypeSet)
|
sortedList = list(_enumTypeSet)
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sortedList.sort(cmp=lambda a, b: cmp(a._name, b._name))
|
sortedList.sort(key=lambda x: x._name)
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for t in sortedList:
|
for t in sortedList:
|
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f.write("%s\n" % t._toVHDL())
|
f.write("%s\n" % t._toVHDL())
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f.write("\n")
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f.write("\n")
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@ -926,6 +926,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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fn = node.func
|
fn = node.func
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# assert isinstance(fn, astNode.Name)
|
# assert isinstance(fn, astNode.Name)
|
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f = self.getObj(fn)
|
f = self.getObj(fn)
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|
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|
if f is print:
|
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|
self.visit_Print(node)
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|
return
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|
|
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fname = ''
|
fname = ''
|
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pre, suf = '', ''
|
pre, suf = '', ''
|
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opening, closing = '(', ')'
|
opening, closing = '(', ')'
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@ -1243,6 +1248,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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for stmt in node.body:
|
for stmt in node.body:
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self.visit(stmt)
|
self.visit(stmt)
|
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|
|
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|
def visit_NameConstant(self, node):
|
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|
node.id = str(node.value)
|
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|
self.getName(node)
|
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|
|
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def visit_Name(self, node):
|
def visit_Name(self, node):
|
||||||
if isinstance(node.ctx, ast.Store):
|
if isinstance(node.ctx, ast.Store):
|
||||||
self.setName(node)
|
self.setName(node)
|
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@ -1975,7 +1984,7 @@ def inferVhdlObj(obj):
|
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if (isinstance(obj, _Signal) and obj._type is intbv) or \
|
if (isinstance(obj, _Signal) and obj._type is intbv) or \
|
||||||
isinstance(obj, intbv):
|
isinstance(obj, intbv):
|
||||||
ls = getattr(obj, 'lenStr', False)
|
ls = getattr(obj, 'lenStr', False)
|
||||||
if obj.min < 0:
|
if obj.min is None or obj.min < 0:
|
||||||
vhd = vhd_signed(size=len(obj), lenStr=ls)
|
vhd = vhd_signed(size=len(obj), lenStr=ls)
|
||||||
else:
|
else:
|
||||||
vhd = vhd_unsigned(size=len(obj), lenStr=ls)
|
vhd = vhd_unsigned(size=len(obj), lenStr=ls)
|
||||||
@ -2101,6 +2110,10 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
|||||||
self.tree.vardict[var] = _loopInt(-1)
|
self.tree.vardict[var] = _loopInt(-1)
|
||||||
self.generic_visit(node)
|
self.generic_visit(node)
|
||||||
|
|
||||||
|
def visit_NameConstant(self, node):
|
||||||
|
node.vhd = inferVhdlObj(node.value)
|
||||||
|
node.vhdOri = copy(node.vhd)
|
||||||
|
|
||||||
def visit_Name(self, node):
|
def visit_Name(self, node):
|
||||||
if node.id in self.tree.vardict:
|
if node.id in self.tree.vardict:
|
||||||
node.obj = self.tree.vardict[node.id]
|
node.obj = self.tree.vardict[node.id]
|
||||||
|
@ -39,7 +39,7 @@ import warnings
|
|||||||
|
|
||||||
import myhdl
|
import myhdl
|
||||||
from myhdl import *
|
from myhdl import *
|
||||||
from myhdl._compat import integer_types, class_types
|
from myhdl._compat import integer_types, class_types, PY2
|
||||||
from myhdl import ToVerilogError, ToVerilogWarning
|
from myhdl import ToVerilogError, ToVerilogWarning
|
||||||
from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo,
|
from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo,
|
||||||
_UserVerilogCode, _userCodeMap)
|
_UserVerilogCode, _userCodeMap)
|
||||||
@ -175,7 +175,7 @@ class _ToVerilogConvertor(object):
|
|||||||
|
|
||||||
# build portmap for cosimulation
|
# build portmap for cosimulation
|
||||||
portmap = {}
|
portmap = {}
|
||||||
for n, s in intf.argdict.iteritems():
|
for n, s in intf.argdict.items():
|
||||||
if hasattr(s, 'driver'): portmap[n] = s.driver()
|
if hasattr(s, 'driver'): portmap[n] = s.driver()
|
||||||
else: portmap[n] = s
|
else: portmap[n] = s
|
||||||
self.portmap = portmap
|
self.portmap = portmap
|
||||||
@ -443,6 +443,12 @@ opmap = {
|
|||||||
ast.Or : '||',
|
ast.Or : '||',
|
||||||
}
|
}
|
||||||
|
|
||||||
|
nameconstant_map = {
|
||||||
|
True: "1'b1",
|
||||||
|
False: "0'b1",
|
||||||
|
None: "'bz"
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||||
@ -716,6 +722,11 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
|||||||
fn = node.func
|
fn = node.func
|
||||||
# assert isinstance(fn, astNode.Name)
|
# assert isinstance(fn, astNode.Name)
|
||||||
f = self.getObj(fn)
|
f = self.getObj(fn)
|
||||||
|
|
||||||
|
if f is print:
|
||||||
|
self.visit_Print(node)
|
||||||
|
return
|
||||||
|
|
||||||
opening, closing = '(', ')'
|
opening, closing = '(', ')'
|
||||||
if f is bool:
|
if f is bool:
|
||||||
self.write("(")
|
self.write("(")
|
||||||
@ -982,6 +993,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
|||||||
def visit_ListComp(self, node):
|
def visit_ListComp(self, node):
|
||||||
pass # do nothing
|
pass # do nothing
|
||||||
|
|
||||||
|
def visit_NameConstant(self, node):
|
||||||
|
self.write(nameconstant_map[node.obj])
|
||||||
|
|
||||||
def visit_Name(self, node):
|
def visit_Name(self, node):
|
||||||
if isinstance(node.ctx, ast.Store):
|
if isinstance(node.ctx, ast.Store):
|
||||||
self.setName(node)
|
self.setName(node)
|
||||||
@ -992,16 +1006,14 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
|||||||
self.write(node.id)
|
self.write(node.id)
|
||||||
|
|
||||||
def getName(self, node):
|
def getName(self, node):
|
||||||
|
n = node.id
|
||||||
|
if PY2 and n in ('True', 'False', 'None'):
|
||||||
|
self.visit_NameConstant(node)
|
||||||
|
return
|
||||||
|
|
||||||
addSignBit = False
|
addSignBit = False
|
||||||
isMixedExpr = (not node.signed) and (self.context == _context.SIGNED)
|
isMixedExpr = (not node.signed) and (self.context == _context.SIGNED)
|
||||||
n = node.id
|
if n in self.tree.vardict:
|
||||||
if n == 'False':
|
|
||||||
s = "1'b0"
|
|
||||||
elif n == 'True':
|
|
||||||
s = "1'b1"
|
|
||||||
elif n == 'None':
|
|
||||||
s = "'bz"
|
|
||||||
elif n in self.tree.vardict:
|
|
||||||
addSignBit = isMixedExpr
|
addSignBit = isMixedExpr
|
||||||
s = n
|
s = n
|
||||||
elif n in self.tree.argnames:
|
elif n in self.tree.argnames:
|
||||||
|
@ -152,7 +152,7 @@ class _VerificationClass(object):
|
|||||||
print("Analysis succeeded", file=sys.stderr)
|
print("Analysis succeeded", file=sys.stderr)
|
||||||
return 0
|
return 0
|
||||||
|
|
||||||
f = tempfile.TemporaryFile()
|
f = tempfile.TemporaryFile(mode='w+t')
|
||||||
sys.stdout = f
|
sys.stdout = f
|
||||||
sim = Simulation(inst)
|
sim = Simulation(inst)
|
||||||
sim.run()
|
sim.run()
|
||||||
@ -174,7 +174,7 @@ class _VerificationClass(object):
|
|||||||
print("Elaboration failed", file=sys.stderr)
|
print("Elaboration failed", file=sys.stderr)
|
||||||
return ret
|
return ret
|
||||||
|
|
||||||
g = tempfile.TemporaryFile()
|
g = tempfile.TemporaryFile(mode='w+t')
|
||||||
#print(simulate)
|
#print(simulate)
|
||||||
ret = subprocess.call(simulate, stdout=g, shell=True)
|
ret = subprocess.call(simulate, stdout=g, shell=True)
|
||||||
# if ret != 0:
|
# if ret != 0:
|
||||||
|
@ -13,13 +13,13 @@ def bench_SliceSignal():
|
|||||||
for i in range(N):
|
for i in range(N):
|
||||||
s.next = i
|
s.next = i
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print int(a)
|
print(int(a))
|
||||||
print int(b)
|
print(int(b))
|
||||||
print int(c)
|
print(int(c))
|
||||||
print d
|
print(d)
|
||||||
print e
|
print(e)
|
||||||
print f
|
print(f)
|
||||||
print g
|
print(g)
|
||||||
|
|
||||||
return check
|
return check
|
||||||
|
|
||||||
@ -52,7 +52,7 @@ def bench_ConcatSignal():
|
|||||||
c.next = k
|
c.next = k
|
||||||
d.next = m
|
d.next = m
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print s
|
print(s)
|
||||||
|
|
||||||
return check
|
return check
|
||||||
|
|
||||||
@ -78,15 +78,15 @@ def bench_TristateSignal():
|
|||||||
#print s
|
#print s
|
||||||
a.next = 1
|
a.next = 1
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print s
|
print(s)
|
||||||
a.next = None
|
a.next = None
|
||||||
b.next = 122
|
b.next = 122
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print s
|
print(s)
|
||||||
b.next = None
|
b.next = None
|
||||||
c.next = 233
|
c.next = 233
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print s
|
print(s)
|
||||||
c.next = None
|
c.next = None
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
#print s
|
#print s
|
||||||
@ -129,7 +129,7 @@ def bench_permute(conv=False):
|
|||||||
for i in range(2**len(a)):
|
for i in range(2**len(a)):
|
||||||
a.next = i
|
a.next = i
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print x, a
|
print("%d %d" % (x, a))
|
||||||
assert x[2] == a[0]
|
assert x[2] == a[0]
|
||||||
assert x[1] == a[2]
|
assert x[1] == a[2]
|
||||||
assert x[0] == a[1]
|
assert x[0] == a[1]
|
||||||
|
@ -56,7 +56,7 @@ def bench_adapter(conv=False):
|
|||||||
assert o_err[1] == (i_err[2] | i_err[3] | i_err[4] | i_err[5])
|
assert o_err[1] == (i_err[2] | i_err[3] | i_err[4] | i_err[5])
|
||||||
assert o_err[2] == i_err[1]
|
assert o_err[2] == i_err[1]
|
||||||
assert o_err[3] == i_err[0]
|
assert o_err[3] == i_err[0]
|
||||||
print o_err
|
print(o_err)
|
||||||
|
|
||||||
return dut, stimulus
|
return dut, stimulus
|
||||||
|
|
||||||
|
@ -60,7 +60,7 @@ def bin2grayBench(width, bin2gray):
|
|||||||
#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
|
#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
|
||||||
#print bin(G, width)
|
#print bin(G, width)
|
||||||
#print bin(G_v, width)
|
#print bin(G_v, width)
|
||||||
print "%d" % G
|
print("%d" % G)
|
||||||
|
|
||||||
|
|
||||||
return stimulus, bin2gray_inst
|
return stimulus, bin2gray_inst
|
||||||
|
@ -70,7 +70,7 @@ def bench_case(map_case, N):
|
|||||||
for i in range(N):
|
for i in range(N):
|
||||||
a.next = i
|
a.next = i
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print z
|
print(z)
|
||||||
|
|
||||||
return stimulus, inst
|
return stimulus, inst
|
||||||
|
|
||||||
|
@ -166,11 +166,11 @@ def DecBench(dec):
|
|||||||
def check():
|
def check():
|
||||||
yield reset.negedge
|
yield reset.negedge
|
||||||
yield reset.posedge
|
yield reset.posedge
|
||||||
print count
|
print(count)
|
||||||
while 1:
|
while 1:
|
||||||
yield clock.posedge
|
yield clock.posedge
|
||||||
yield delay(1)
|
yield delay(1)
|
||||||
print count
|
print(count)
|
||||||
|
|
||||||
dec_inst = dec(count, enable, clock, reset, n=n)
|
dec_inst = dec(count, enable, clock, reset, n=n)
|
||||||
|
|
||||||
|
@ -102,7 +102,7 @@ def FSMBench(FramerCtrl, t_State):
|
|||||||
yield clk.posedge
|
yield clk.posedge
|
||||||
while True:
|
while True:
|
||||||
yield clk.negedge
|
yield clk.negedge
|
||||||
print "negedge"
|
print("negedge")
|
||||||
# in the end, this should work
|
# in the end, this should work
|
||||||
# print state
|
# print state
|
||||||
|
|
||||||
|
@ -117,9 +117,9 @@ def HecCalculator_v(name, hec, header):
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
headers = [ 0x00000000L,
|
headers = [ 0x00000000,
|
||||||
0x01234567L,
|
0x01234567,
|
||||||
0xbac6f4caL
|
0xbac6f4ca
|
||||||
]
|
]
|
||||||
|
|
||||||
headers.extend([randrange(2**32-1) for i in range(10)])
|
headers.extend([randrange(2**32-1) for i in range(10)])
|
||||||
@ -139,7 +139,7 @@ def HecBench(HecCalculator):
|
|||||||
for i in range(len(headers)):
|
for i in range(len(headers)):
|
||||||
header.next = headers[i]
|
header.next = headers[i]
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print hec
|
print(hec)
|
||||||
|
|
||||||
return stimulus, heccalc_inst
|
return stimulus, heccalc_inst
|
||||||
|
|
||||||
|
@ -157,7 +157,7 @@ def IncBench(inc):
|
|||||||
yield clock.negedge
|
yield clock.negedge
|
||||||
while True:
|
while True:
|
||||||
yield clock.negedge
|
yield clock.negedge
|
||||||
print count
|
print(count)
|
||||||
|
|
||||||
return inc_inst, clockgen, monitor
|
return inc_inst, clockgen, monitor
|
||||||
|
|
||||||
|
@ -51,7 +51,7 @@ def PlainIntbv():
|
|||||||
@instance
|
@instance
|
||||||
def logic():
|
def logic():
|
||||||
|
|
||||||
print "Plain Instance Test"
|
print("Plain Instance Test")
|
||||||
|
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
# intbv with positive range, pos number, and msb not set, return signed()
|
# intbv with positive range, pos number, and msb not set, return signed()
|
||||||
@ -208,7 +208,7 @@ def SlicedSigned():
|
|||||||
def logic():
|
def logic():
|
||||||
b = intbv(4, min=-8, max=8)
|
b = intbv(4, min=-8, max=8)
|
||||||
a = intbv(4, min=-8, max=8)
|
a = intbv(4, min=-8, max=8)
|
||||||
print "SLicedSigned test"
|
print("SLicedSigned test")
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
b[:] = a[4:]
|
b[:] = a[4:]
|
||||||
assert b == 4
|
assert b == 4
|
||||||
@ -228,7 +228,7 @@ def SignedConcat():
|
|||||||
|
|
||||||
@instance
|
@instance
|
||||||
def logic():
|
def logic():
|
||||||
print "Signed Concat test"
|
print("Signed Concat test")
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
|
|
||||||
# concat 3 bits
|
# concat 3 bits
|
||||||
|
@ -32,7 +32,7 @@ def intbv2list():
|
|||||||
a.next = i
|
a.next = i
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
assert z == a
|
assert z == a
|
||||||
print a
|
print(a)
|
||||||
raise StopSimulation
|
raise StopSimulation
|
||||||
|
|
||||||
return extract, assemble, stimulus
|
return extract, assemble, stimulus
|
||||||
@ -186,7 +186,7 @@ def processlist(case, inv):
|
|||||||
a.next = i
|
a.next = i
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
assert z == ~a
|
assert z == ~a
|
||||||
print z
|
print(z)
|
||||||
raise StopSimulation
|
raise StopSimulation
|
||||||
|
|
||||||
return case_inst, stimulus
|
return case_inst, stimulus
|
||||||
@ -225,7 +225,7 @@ def unsigned():
|
|||||||
a[0].next = 2
|
a[0].next = 2
|
||||||
a[1].next = 5
|
a[1].next = 5
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print z
|
print(z)
|
||||||
|
|
||||||
return logic, stimulus
|
return logic, stimulus
|
||||||
|
|
||||||
@ -247,7 +247,7 @@ def signed():
|
|||||||
a[0].next = 2
|
a[0].next = 2
|
||||||
a[1].next = -5
|
a[1].next = -5
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print z
|
print(z)
|
||||||
|
|
||||||
return logic, stimulus
|
return logic, stimulus
|
||||||
|
|
||||||
@ -270,7 +270,7 @@ def mixed():
|
|||||||
a[0].next = -6
|
a[0].next = -6
|
||||||
b[2].next = 15
|
b[2].next = 15
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print z
|
print(z)
|
||||||
|
|
||||||
return logic, stimulus
|
return logic, stimulus
|
||||||
|
|
||||||
|
@ -291,7 +291,7 @@ def LoopBench(LoopTest):
|
|||||||
for i in range(100):
|
for i in range(100):
|
||||||
a.next = data[i]
|
a.next = data[i]
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print z
|
print(z)
|
||||||
|
|
||||||
return stimulus, looptest_inst
|
return stimulus, looptest_inst
|
||||||
|
|
||||||
|
@ -136,7 +136,7 @@ def ObjBench(hObj):
|
|||||||
x.next = nx
|
x.next = nx
|
||||||
yield clk.posedge
|
yield clk.posedge
|
||||||
yield clk.posedge
|
yield clk.posedge
|
||||||
print "x %d y %d" % (x, y)
|
print("x %d y %d" % (x, y))
|
||||||
assert x == nx
|
assert x == nx
|
||||||
assert y == ny
|
assert y == ny
|
||||||
raise StopSimulation
|
raise StopSimulation
|
||||||
|
@ -40,19 +40,19 @@ def NonlocalBench():
|
|||||||
yield clk.negedge
|
yield clk.negedge
|
||||||
reset.next = 1
|
reset.next = 1
|
||||||
yield clk.negedge
|
yield clk.negedge
|
||||||
print qout
|
print(qout)
|
||||||
assert qout == ONE
|
assert qout == ONE
|
||||||
reset.next = 0
|
reset.next = 0
|
||||||
for i in range(100):
|
for i in range(100):
|
||||||
yield clk.negedge
|
yield clk.negedge
|
||||||
print qout
|
print(qout)
|
||||||
init.next = 1
|
init.next = 1
|
||||||
yield clk.negedge
|
yield clk.negedge
|
||||||
assert qout == ALL_ONES
|
assert qout == ALL_ONES
|
||||||
print qout
|
print(qout)
|
||||||
init.next = 0
|
init.next = 0
|
||||||
for i in range(300):
|
for i in range(300):
|
||||||
print qout
|
print(qout)
|
||||||
raise StopSimulation()
|
raise StopSimulation()
|
||||||
|
|
||||||
return scrambler, clkgen, stimulus
|
return scrambler, clkgen, stimulus
|
||||||
|
@ -15,40 +15,39 @@ def NumassBench():
|
|||||||
|
|
||||||
@instance
|
@instance
|
||||||
def check():
|
def check():
|
||||||
p.next = 0
|
p.next = 0
|
||||||
q.next = 0
|
q.next = 0
|
||||||
r.next = 0
|
r.next = 0
|
||||||
s.next = 0
|
s.next = 0
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print p, q, r ,s
|
print("%d %d %d %d" % (p, q, r, s))
|
||||||
p.next = 1
|
p.next = 1
|
||||||
q.next = 1
|
q.next = 1
|
||||||
r.next = 1
|
r.next = 1
|
||||||
s.next = 1
|
s.next = 1
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print p, q, r ,s
|
print("%d %d %d %d" % (p, q, r, s))
|
||||||
p.next = 2
|
p.next = 2
|
||||||
q.next = 2
|
q.next = 2
|
||||||
r.next = -2
|
r.next = -2
|
||||||
s.next = -2
|
s.next = -2
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print p, q, r ,s
|
print("%d %d %d %d" % (p, q, r, s))
|
||||||
p.next = 255
|
p.next = 255
|
||||||
q.next = 246836311517
|
q.next = 246836311517
|
||||||
r.next = 255
|
r.next = 255
|
||||||
s.next = -246836311517
|
s.next = -246836311517
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
|
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0]))
|
||||||
p.next = 254
|
p.next = 254
|
||||||
q.next = PBIGINT
|
q.next = PBIGINT
|
||||||
r.next = -256
|
r.next = -256
|
||||||
s.next = NBIGINT
|
s.next = NBIGINT
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
|
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0]))
|
||||||
|
|
||||||
return check
|
return check
|
||||||
|
|
||||||
|
|
||||||
def test_numass():
|
def test_numass():
|
||||||
assert conversion.verify(NumassBench) == 0
|
assert conversion.verify(NumassBench) == 0
|
||||||
|
|
||||||
|
@ -21,47 +21,47 @@ def PrintBench():
|
|||||||
i2[:] = -7
|
i2[:] = -7
|
||||||
si2.next = -5
|
si2.next = -5
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print
|
print('')
|
||||||
print i1
|
print(i1)
|
||||||
print i2
|
print(i2)
|
||||||
print i1, i2
|
print("%d %d" % (i1, i2))
|
||||||
print si1
|
print(si1)
|
||||||
print si2
|
print(si2)
|
||||||
|
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "This is a test"
|
print("This is a test")
|
||||||
|
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print int(b)
|
print(int(b))
|
||||||
print int(sb)
|
print(int(sb))
|
||||||
|
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "i1 is %s" % i1
|
print("i1 is %s" % i1)
|
||||||
|
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "i1 is %s, i2 is %s" % (i1, i2)
|
print("i1 is %s, i2 is %s" % (i1, i2))
|
||||||
print "i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2)
|
print("i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2))
|
||||||
print "i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2)
|
print("i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2))
|
||||||
print b
|
print(b)
|
||||||
#print "%% %s" % i1
|
#print "%% %s" % i1
|
||||||
|
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print state
|
print(state)
|
||||||
print "the state is %s" % state
|
print("the state is %s" % state)
|
||||||
print "the state is %s" % (state,)
|
print("the state is %s" % (state,))
|
||||||
print "i1 is %s and the state is %s" % (i1, state)
|
print("i1 is %s and the state is %s" % (i1, state))
|
||||||
|
|
||||||
# ord test
|
# ord test
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print ord('y')
|
print(ord('y'))
|
||||||
print ord('2')
|
print(ord('2'))
|
||||||
|
|
||||||
# signed
|
# signed
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print i1.signed()
|
print(i1.signed())
|
||||||
print i2.signed()
|
print(i2.signed())
|
||||||
print si1.signed()
|
print(si1.signed())
|
||||||
print si2.signed()
|
print(si2.signed())
|
||||||
|
|
||||||
return logic
|
return logic
|
||||||
|
|
||||||
@ -76,7 +76,7 @@ def PrintError1():
|
|||||||
def logic():
|
def logic():
|
||||||
i1 = intbv(12)[8:]
|
i1 = intbv(12)[8:]
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "floating point %f end" % i1
|
print("floating point %f end" % i1)
|
||||||
return logic
|
return logic
|
||||||
|
|
||||||
def testPrintError1():
|
def testPrintError1():
|
||||||
@ -92,7 +92,7 @@ def PrintError2():
|
|||||||
def logic():
|
def logic():
|
||||||
i1 = intbv(12)[8:]
|
i1 = intbv(12)[8:]
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "begin %s %s end" % i1
|
print("begin %s %s end" % i1)
|
||||||
return logic
|
return logic
|
||||||
|
|
||||||
def testPrintError2():
|
def testPrintError2():
|
||||||
@ -109,7 +109,7 @@ def PrintError3():
|
|||||||
i1 = intbv(12)[8:]
|
i1 = intbv(12)[8:]
|
||||||
i2 = intbv(13)[8:]
|
i2 = intbv(13)[8:]
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "begin %s end" % (i1, i2)
|
print("begin %s end" % (i1, i2))
|
||||||
return logic
|
return logic
|
||||||
|
|
||||||
def testPrintError3():
|
def testPrintError3():
|
||||||
@ -125,7 +125,7 @@ def PrintError4():
|
|||||||
def logic():
|
def logic():
|
||||||
i1 = intbv(12)[8:]
|
i1 = intbv(12)[8:]
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "%10s" % i1
|
print("%10s" % i1)
|
||||||
return logic
|
return logic
|
||||||
|
|
||||||
def testPrintError4():
|
def testPrintError4():
|
||||||
@ -141,7 +141,7 @@ def PrintError5():
|
|||||||
def logic():
|
def logic():
|
||||||
i1 = intbv(12)[8:]
|
i1 = intbv(12)[8:]
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
print "%-10s" % i1
|
print("%-10s" % i1)
|
||||||
return logic
|
return logic
|
||||||
|
|
||||||
def testPrintError5():
|
def testPrintError5():
|
||||||
|
@ -117,7 +117,7 @@ def RamBench(ram, depth=128):
|
|||||||
yield clk.posedge
|
yield clk.posedge
|
||||||
yield delay(1)
|
yield delay(1)
|
||||||
assert dout == i
|
assert dout == i
|
||||||
print dout
|
print(dout)
|
||||||
raise StopSimulation()
|
raise StopSimulation()
|
||||||
|
|
||||||
@instance
|
@instance
|
||||||
|
@ -73,7 +73,7 @@ def RomBench(rom):
|
|||||||
yield delay(1)
|
yield delay(1)
|
||||||
if __debug__:
|
if __debug__:
|
||||||
assert dout == ROM[i]
|
assert dout == ROM[i]
|
||||||
print dout
|
print(dout)
|
||||||
raise StopSimulation()
|
raise StopSimulation()
|
||||||
|
|
||||||
@instance
|
@instance
|
||||||
|
@ -55,7 +55,7 @@ def TernaryBench(ternary):
|
|||||||
clk.next = 1
|
clk.next = 1
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
assert dout == (i + 1) % 128
|
assert dout == (i + 1) % 128
|
||||||
print dout
|
print(dout)
|
||||||
clk.next = 0
|
clk.next = 0
|
||||||
yield delay(10)
|
yield delay(10)
|
||||||
|
|
||||||
|
Loading…
x
Reference in New Issue
Block a user