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refactoring
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commit
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@ -105,27 +105,49 @@ class _UserCode(object):
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code = "\n%s\n" % code
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return code
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class _UserVerilog(_UserCode):
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class _UserVerilogCode(_UserCode):
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def raiseError(self, msg, info):
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raise ToVerilogError("Error in user defined Verilog code", msg, info)
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class _UserVhdl(_UserCode):
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class _UserVhdlCode(_UserCode):
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def raiseError(self, msg, info):
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raise ToVHDLError("Error in user defined VHDL code", msg, info)
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_UserVerilogInstance = _UserVerilogCode
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_UserVhdlInstance = _UserVhdlCode
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def _addUserCode(hdl, spec, arg, funcname, frame):
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classMap = {'verilog' : _UserVerilog,
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'vhdl' :_UserVhdl
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def _addUserCode(specs, arg, funcname, frame):
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classMap = {
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'__verilog__' : _UserVerilogCode,
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'__vhdl__' :_UserVhdlCode,
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'verilog_code' : _UserVerilogCode,
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'vhdl_code' :_UserVhdlCode,
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'verilog_code' : _UserVerilogInstance,
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'vhdl_code' :_UserVhdlInstance,
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}
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code = frame.f_locals[spec]
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namespace = frame.f_globals.copy()
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namespace.update(frame.f_locals)
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sourcefile = inspect.getsourcefile(frame)
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sourceline = inspect.getsourcelines(frame)[1]
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assert id(arg) not in _userCodeMap[hdl]
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_userCodeMap[hdl][id(arg)] = classMap[hdl](code, namespace, sourcefile, funcname, sourceline)
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for hdl in _userCodeMap:
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oldspec = "__%s__" % hdl
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codespec = "%s_code" % hdl
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instancespec = "%s_instance" % hdl
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spec = None
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# XXX add warning logic
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if instancespec in specs:
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spec = instancespec
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elif codespec in specs:
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spec = codespec
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elif oldspec in specs:
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spec = oldspec
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if spec:
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assert id(arg) not in _userCodeMap[hdl]
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code = specs[spec]
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_userCodeMap[hdl][id(arg)] = classMap[spec](code, namespace, sourcefile, funcname, sourceline)
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class _CallFuncVisitor(object):
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@ -212,10 +234,19 @@ class _HierExtr(object):
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if not self.skip:
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isGenSeq = _isGenSeq(arg)
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if isGenSeq:
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specs = {}
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for hdl in _userCodeMap:
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spec = "__%s__" % hdl
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if spec in frame.f_locals:
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_addUserCode(hdl, spec, arg, funcname, frame)
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if spec in frame.f_locals and frame.f_locals[spec]:
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specs[spec] = frame.f_locals[spec]
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spec = "%s_code"
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if func and hasattr(func, spec) and func.spec:
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specs[spec] = func.spec
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spec = "%s_instance"
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if func and hasattr(func, spec) and func.spec:
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specs[spec] = func.spec
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if specs:
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_addUserCode(specs, arg, funcname, frame)
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# building hierarchy only makes sense if there are generators
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if isGenSeq and arg:
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sigdict = {}
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@ -41,7 +41,7 @@ import myhdl
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from myhdl import *
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from myhdl import ToVHDLError, ToVHDLWarning
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from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo,
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_UserVhdl, _userCodeMap)
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_UserVhdlCode, _userCodeMap)
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from myhdl._always_comb import _AlwaysComb
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from myhdl._always import _Always
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@ -60,7 +60,7 @@ _enumTypeList = []
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def _checkArgs(arglist):
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for arg in arglist:
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if not isinstance(arg, (GeneratorType, _Instantiator, _UserVhdl)):
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if not isinstance(arg, (GeneratorType, _Instantiator, _UserVhdlCode)):
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raise ToVHDLError(_error.ArgType, arg)
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def _flatten(*args):
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@ -330,7 +330,7 @@ def _convertGens(genlist, siglist, vfile):
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blockBuf = StringIO()
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funcBuf = StringIO()
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for tree in genlist:
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if isinstance(tree, _UserVhdl):
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if isinstance(tree, _UserVhdlCode):
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blockBuf.write(str(tree))
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continue
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if tree.kind == _kind.ALWAYS:
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@ -3323,7 +3323,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
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def _annotateTypes(genlist):
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for tree in genlist:
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if isinstance(tree, _UserVhdl):
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if isinstance(tree, _UserVhdlCode):
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continue
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v = _AnnotateTypesVisitor(tree)
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v.visit(tree)
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@ -41,7 +41,7 @@ import myhdl
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from myhdl import *
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from myhdl import ToVerilogError, ToVerilogWarning
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from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo,
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_UserVerilog, _userCodeMap)
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_UserVerilogCode, _userCodeMap)
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from myhdl._always_comb import _AlwaysComb
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from myhdl._always import _Always
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@ -57,7 +57,7 @@ _profileFunc = None
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def _checkArgs(arglist):
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for arg in arglist:
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if not isinstance(arg, (GeneratorType, _Instantiator, _UserVerilog)):
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if not isinstance(arg, (GeneratorType, _Instantiator, _UserVerilogCode)):
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raise ToVerilogError(_error.ArgType, arg)
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def _flatten(*args):
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@ -341,7 +341,7 @@ def _convertGens(genlist, vfile):
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blockBuf = StringIO()
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funcBuf = StringIO()
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for tree in genlist:
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if isinstance(tree, _UserVerilog):
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if isinstance(tree, _UserVerilogCode):
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blockBuf.write(str(tree))
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continue
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if tree.kind == _kind.ALWAYS:
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