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https://github.com/myhdl/myhdl.git
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Made VHDL architecture parameterizable with toVHDL.architecture
--HG-- branch : 0.8-dev
This commit is contained in:
parent
c75e762158
commit
5a6351f370
@ -94,7 +94,9 @@ class _ToVHDLConvertor(object):
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"component_declarations",
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"component_declarations",
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"header",
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"header",
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"no_myhdl_header",
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"no_myhdl_header",
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"library"
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"no_myhdl_package",
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"library",
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"architecture"
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)
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)
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def __init__(self):
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def __init__(self):
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@ -102,7 +104,9 @@ class _ToVHDLConvertor(object):
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self.component_declarations = None
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self.component_declarations = None
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self.header = ''
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self.header = ''
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self.no_myhdl_header = False
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self.no_myhdl_header = False
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self.no_myhdl_package = False
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self.library = "work"
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self.library = "work"
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self.architecture = "MyHDL"
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def __call__(self, func, *args, **kwargs):
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def __call__(self, func, *args, **kwargs):
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global _converting
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global _converting
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@ -132,11 +136,13 @@ class _ToVHDLConvertor(object):
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vpath = name + ".vhd"
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vpath = name + ".vhd"
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vfile = open(vpath, 'w')
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vfile = open(vpath, 'w')
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ppath = "pck_myhdl_%s.vhd" % _shortversion
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ppath = "pck_myhdl_%s.vhd" % _shortversion
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pfile = None
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# # write MyHDL package always during development, as it may change
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# # write MyHDL package always during development, as it may change
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# pfile = None
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# pfile = None
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# if not os.path.isfile(ppath):
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# if not os.path.isfile(ppath):
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# pfile = open(ppath, 'w')
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# pfile = open(ppath, 'w')
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pfile = open(ppath, 'w')
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if not self.no_myhdl_package:
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pfile = open(ppath, 'w')
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### initialize properly ###
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### initialize properly ###
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_genUniqueSuffix.reset()
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_genUniqueSuffix.reset()
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@ -154,6 +160,7 @@ class _ToVHDLConvertor(object):
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needPck = len(_enumTypeSet) > 0
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needPck = len(_enumTypeSet) > 0
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lib = self.library
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lib = self.library
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arch = self.architecture
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if pfile:
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if pfile:
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_writeFileHeader(pfile, ppath)
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_writeFileHeader(pfile, ppath)
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@ -163,12 +170,12 @@ class _ToVHDLConvertor(object):
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_writeFileHeader(vfile, vpath)
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_writeFileHeader(vfile, vpath)
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if needPck:
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if needPck:
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_writeCustomPackage(vfile, intf)
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_writeCustomPackage(vfile, intf)
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_writeModuleHeader(vfile, intf, needPck, lib, doc)
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_writeModuleHeader(vfile, intf, needPck, lib, arch, doc)
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_writeFuncDecls(vfile)
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_writeFuncDecls(vfile)
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_writeSigDecls(vfile, intf, siglist, memlist)
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_writeSigDecls(vfile, intf, siglist, memlist)
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_writeCompDecls(vfile, compDecls)
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_writeCompDecls(vfile, compDecls)
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_convertGens(genlist, siglist, memlist, vfile)
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_convertGens(genlist, siglist, memlist, vfile)
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_writeModuleFooter(vfile)
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_writeModuleFooter(vfile, arch)
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vfile.close()
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vfile.close()
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# tbfile.close()
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# tbfile.close()
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@ -187,6 +194,8 @@ class _ToVHDLConvertor(object):
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self.component_declarations = None
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self.component_declarations = None
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self.header = ''
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self.header = ''
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self.no_myhdl_header = False
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self.no_myhdl_header = False
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self.no_myhdl_package = False
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self.architecture = "MyHDL"
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return h.top
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return h.top
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@ -225,7 +234,7 @@ def _writeCustomPackage(f, intf):
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print >> f
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print >> f
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def _writeModuleHeader(f, intf, needPck, lib, doc):
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def _writeModuleHeader(f, intf, needPck, lib, arch, doc):
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print >> f, "library IEEE;"
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print >> f, "library IEEE;"
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print >> f, "use IEEE.std_logic_1164.all;"
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print >> f, "use IEEE.std_logic_1164.all;"
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print >> f, "use IEEE.numeric_std.all;"
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print >> f, "use IEEE.numeric_std.all;"
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@ -272,11 +281,10 @@ def _writeModuleHeader(f, intf, needPck, lib, doc):
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print >> f, "end entity %s;" % intf.name
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print >> f, "end entity %s;" % intf.name
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print >> f, doc
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print >> f, doc
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print >> f
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print >> f
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print >> f, "architecture MyHDL of %s is" % intf.name
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print >> f, "architecture %s of %s is" % (arch, intf.name)
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print >> f
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print >> f
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def _writeFuncDecls(f):
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def _writeFuncDecls(f):
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return
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return
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# print >> f, package
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# print >> f, package
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@ -333,8 +341,8 @@ def _writeCompDecls(f, compDecls):
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if compDecls is not None:
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if compDecls is not None:
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print >> f, compDecls
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print >> f, compDecls
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def _writeModuleFooter(f):
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def _writeModuleFooter(f, arch):
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print >> f, "end architecture MyHDL;"
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print >> f, "end architecture %s;" % arch
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