From 5aad5f325449affa3f81bcaeaccfe38b4c9151ba Mon Sep 17 00:00:00 2001
From: Jan Decaluwe <jan@jandecaluwe.com>
Date: Fri, 25 May 2012 11:09:22 +0200
Subject: [PATCH] Solved bug 3529686

---
 myhdl/conversion/_analyze.py        |  2 +-
 myhdl/test/bugs/test_bug_3529686.py | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+), 1 deletion(-)
 create mode 100644 myhdl/test/bugs/test_bug_3529686.py

diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py
index d4c372fd..5c54b633 100644
--- a/myhdl/conversion/_analyze.py
+++ b/myhdl/conversion/_analyze.py
@@ -759,7 +759,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
             if not hasattr(test, 'case'):
                 return
             var, item = test.case
-            if var.obj != var1.obj or type(item) is not type(item1):
+            if var.id != var1.id or type(item) is not type(item1):
                 return
             if item in choices:
                 return
diff --git a/myhdl/test/bugs/test_bug_3529686.py b/myhdl/test/bugs/test_bug_3529686.py
new file mode 100644
index 00000000..70e63925
--- /dev/null
+++ b/myhdl/test/bugs/test_bug_3529686.py
@@ -0,0 +1,25 @@
+from myhdl import *
+
+def bug_3529686(clr, clk, run, ack, serialout):
+
+    @always(clk.posedge, clr.posedge)
+    def fsm():
+        if (clr == 0):
+            serialout.next = 0 
+        else:
+            if (ack == 0):
+                serialout.next = 0
+            elif (run == 1):
+                serialout.next = 1
+
+    return fsm 
+
+
+clr, clk, run, ack, serialout = [Signal(bool()) for i in range(5)]
+
+
+def test_bug_3529686():
+    try:
+        toVHDL(bug_3529686, clr, clk, run, ack, serialout)
+    except:
+        assert False