FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity

No need for type conversion on constants

Browse Source 
--HG--
branch : 0.8-dev
This commit is contained in:
Jan Decaluwe 2013-04-27 10:49:34 +02:00
parent 2fac1b8bde
commit 5b4afee538
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
myhdl/conversion/_toVHDL.py
View File

@ -849,7 +849,8 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
if isinstance(lhs.value, ast.Name):
sig = self.tree.symdict[lhs.value.id]
if not sig._numeric:
convOpen, convClose = "std_logic_vector(", ")"
if not isinstance(rhs, ast.Num):
convOpen, convClose = "std_logic_vector(", ")"
self.write(' <= ')
self.SigAss = False
else: