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mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00

better support for mapping to case statements

This commit is contained in:
Jan Decaluwe 2010-06-22 17:46:44 +02:00
parent 84ee1bd778
commit 5fe347ff13
3 changed files with 27 additions and 15 deletions

View File

@ -899,12 +899,12 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
## arg.target = self.getObj(node.expr)
# detect specialized case for the test
if isinstance(op, ast.Eq) and isinstance(node.left, ast.Name):
n = node.left.id
# check wether it can be a case
if isinstance(arg.obj, EnumItemType):
if isinstance(arg.obj, (EnumItemType, int, long)):
node.case = (node.left, arg.obj)
# check whether it can be part of an edge check
elif n in self.tree.sigdict:
n = node.left.id
if n in self.tree.sigdict:
sig = self.tree.sigdict[n]
v = self.getValue(arg)
if v is not None:
@ -1068,19 +1068,20 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
if not node.tests[1:]:
return
choices = set()
choices.add(item1._index)
choices.add(item1)
for test, suite in node.tests[1:]:
if not hasattr(test, 'case'):
return
var, item = test.case
if var.obj != var1.obj or type(item) is not type(item1):
return
if item._index in choices:
if item in choices:
return
choices.add(item._index)
choices.add(item)
node.isCase = True
node.caseVar = var1
if (len(choices) == item1._nritems) or (node.else_ is not None):
if (len(choices) == len(var1.obj)) or (node.else_ is not None):
node.isFullCase = True

View File

@ -405,6 +405,14 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
def writeline(self, nr=1):
for i in range(nr):
self.buf.write("\n%s" % self.ind)
def IntRepr(self, obj):
if obj >= 0:
s = "%s" % int(obj)
else:
s = "(- %s)" % abs(int(obj))
return s
def inferCast(self, vhd, ori):
pre, suf = "", ""
@ -1578,7 +1586,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.writeline()
item = test.comparators[0].obj
self.write("when ")
self.write(item._toVHDL())
if isinstance(item, EnumItemType):
self.write(item._toVHDL())
else:
self.write(self.IntRepr(item))
self.write(" =>")
self.indent()
self.visit_stmt(suite)
@ -1796,10 +1807,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
s = "'%s'" % int(obj)
elif isinstance(obj, (int, long)):
if isinstance(node.vhd, vhd_int):
if obj >= 0:
s = "%s" % int(obj)
else:
s = "(- %s)" % abs(int(obj))
s = self.IntRepr(obj)
elif isinstance(node.vhd, vhd_std_logic):
s = "'%s'" % int(obj)
else:
@ -2171,7 +2179,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
assert bt
for e in senslist:
if not isinstance(e, bt):
self.raiseError(node, "base type error in sensitivity list")
self.raiseError(ifnode, "base type error in sensitivity list")
if len(senslist) >= 2 and bt == _WaiterList:
# ifnode = node.code.nodes[0]
# print ifnode

View File

@ -1038,7 +1038,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
if self.context == _context.PRINT:
self.write('"%s"' % node.n)
else:
self.write(node.n)
self.write(self.IntRepr(node.n))
def visit_Str(self, node):
if self.context == _context.PRINT:
@ -1244,7 +1244,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
for test, suite in node.tests:
self.writeline()
item = test.comparators[0].obj
self.write(item._toVerilog(dontcare=True))
if isinstance(item, EnumItemType):
self.write(item._toVerilog(dontcare=True))
else:
self.write(self.IntRepr(item))
self.write(": begin")
self.indent()
self.visit_stmt(suite)