FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

0.4.1

Browse Source
This commit is contained in:
jand 2004-12-28 17:14:39 +00:00
parent 022998dc9c
commit 5fef54e6c7
1 changed files with 15 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
CHANGES.txt
View File

@ -1,7 +1,21 @@
Release 0.4.1 29-Dec-2004
-------------------------
* Maintenance release that solves most outstanding issues
and implements some feature requests.
See the SourceForge Bug and RFE Trackers for details.
(Use the group 'MyHDL 0.4' to find the relevant issues.)
More info can also be found on the mailing list.
* Added cosimulation support for the cver Verilog simulator.
Note: the documentation was not modified in this release.
Release 0.4 4-Feb-2004
----------------------
* Conversion to Verilog to provice a path to implementation
* Conversion to Verilog to provide a path to implementation
For details, consult the whatsnew04.* documents available
in various formats under doc/.