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used 0.6 version number for examples

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This commit is contained in:
Jan Decaluwe 2008-11-23 11:36:16 +01:00
parent f18a2664bf
commit 611457033e
14 changed files with 35 additions and 35 deletions
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4
example/manual/FramerCtrl.v
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@ -1,6 +1,6 @@
// File: FramerCtrl.v
// Generated by MyHDL 0.6dev10
// Date: Sat Nov 22 22:39:38 2008
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008
`timescale 1ns/10ps

6
example/manual/FramerCtrl.vhd
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@ -1,6 +1,6 @@
-- File: FramerCtrl.vhd
-- Generated by MyHDL 0.6dev10
-- Date: Sat Nov 22 22:39:38 2008
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
package pck_FramerCtrl is
@ -19,7 +19,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06dev10.all;
use work.pck_myhdl_06.all;
use work.pck_FramerCtrl.all;

4
example/manual/GrayIncReg.v
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@ -1,6 +1,6 @@
// File: GrayIncReg.v
// Generated by MyHDL 0.6dev10
// Date: Sat Nov 22 22:39:37 2008
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008
`timescale 1ns/10ps

6
example/manual/GrayIncReg.vhd
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@ -1,13 +1,13 @@
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.6dev10
-- Date: Sat Nov 22 22:39:37 2008
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06dev10.all;
use work.pck_myhdl_06.all;
entity GrayIncReg is
port (

4
example/manual/Inc.v
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@ -1,6 +1,6 @@
// File: Inc.v
// Generated by MyHDL 0.6dev10
// Date: Sat Nov 22 22:39:37 2008
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008
`timescale 1ns/10ps

6
example/manual/Inc.vhd
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@ -1,13 +1,13 @@
-- File: Inc.vhd
-- Generated by MyHDL 0.6dev10
-- Date: Sat Nov 22 22:39:37 2008
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06dev10.all;
use work.pck_myhdl_06.all;
entity Inc is
port (

4
example/manual/bin2gray.v
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@ -1,6 +1,6 @@
// File: bin2gray.v
// Generated by MyHDL 0.6dev10
// Date: Sat Nov 22 22:39:37 2008
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008
`timescale 1ns/10ps

6
example/manual/bin2gray.vhd
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@ -1,13 +1,13 @@
-- File: bin2gray.vhd
-- Generated by MyHDL 0.6dev10
-- Date: Sat Nov 22 22:39:37 2008
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06dev10.all;
use work.pck_myhdl_06.all;
entity bin2gray is
port (

4
example/manual/inc_comb.v
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@ -1,6 +1,6 @@
// File: inc_comb.v
// Generated by MyHDL 0.6dev10
// Date: Sat Nov 22 22:39:38 2008
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008
`timescale 1ns/10ps

6
example/manual/inc_comb.vhd
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@ -1,13 +1,13 @@
-- File: inc_comb.vhd
-- Generated by MyHDL 0.6dev10
-- Date: Sat Nov 22 22:39:38 2008
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06dev10.all;
use work.pck_myhdl_06.all;
entity inc_comb is
port (

6
example/manual/ram.vhd
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@ -1,13 +1,13 @@
-- File: ram.vhd
-- Generated by MyHDL 0.6dev10
-- Date: Sat Nov 22 22:39:38 2008
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06dev10.all;
use work.pck_myhdl_06.all;
entity ram is
port (

4
example/manual/ram_1.v
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@ -1,6 +1,6 @@
// File: ram_1.v
// Generated by MyHDL 0.6dev10
// Date: Sat Nov 22 22:39:38 2008
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008
`timescale 1ns/10ps

4
example/manual/rom.v
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@ -1,6 +1,6 @@
// File: rom.v
// Generated by MyHDL 0.6dev10
// Date: Sat Nov 22 22:39:38 2008
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008
`timescale 1ns/10ps

6
example/manual/rom.vhd
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@ -1,13 +1,13 @@
-- File: rom.vhd
-- Generated by MyHDL 0.6dev10
-- Date: Sat Nov 22 22:39:38 2008
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06dev10.all;
use work.pck_myhdl_06.all;
entity rom is
port (