diff --git a/myhdl/_misc.py b/myhdl/_misc.py
index 334ff598..ae2ad787 100644
--- a/myhdl/_misc.py
+++ b/myhdl/_misc.py
@@ -24,36 +24,12 @@ instances -- function that returns instances in a generator function
 downrange -- function that returns a downward range
 
 """
-from sys import version_info
 import inspect
 
 from myhdl._Cosimulation import Cosimulation
 from myhdl._instance import _Instantiator
 
 
-# 06-03-2021 as the Python gang likes to keep breaking code with about every release ...
-# we need a way to keep track
-def ispythonversion(major, minor):
-    ''' 
-        compares the actual version with the given major, minor
-        returns 
-            -1 if smaller
-            0 if exact
-            1 if greater
-    '''
-    if version_info.major < major:
-        return -1
-    elif version_info.major == major:
-        if version_info.minor < minor:
-            return -1
-        elif version_info.minor == minor:
-            return 0
-        else:
-            return 1
-    else:
-        return 1
-
-
 def _isGenSeq(obj):
     from myhdl._block import _Block
     if isinstance(obj, (Cosimulation, _Instantiator, _Block)):
diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py
index 3f6f7775..f76b3134 100644
--- a/myhdl/conversion/_analyze.py
+++ b/myhdl/conversion/_analyze.py
@@ -16,7 +16,6 @@
 #  You should have received a copy of the GNU Lesser General Public
 #  License along with this library; if not, write to the Free Software
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-from myhdl._misc import ispythonversion
 
 """ MyHDL conversion analysis module.
 
@@ -977,7 +976,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
     def accessIndex(self, node):
         self.visit(node.value)
         self.access = _access.INPUT
-        if ispythonversion(3, 9) >= 0:
+        if sys.version_info >= (3, 9, 0):  # Python 3.9+: no ast.Index wrapper
             self.visit(node.slice)
         else:
             self.visit(node.slice.value)
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index d6871e2c..379aaedf 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -50,7 +50,7 @@ from myhdl._modbv import modbv
 from myhdl._simulator import now
 from myhdl._concat import concat
 from myhdl._delay import delay
-from myhdl._misc import downrange, ispythonversion
+from myhdl._misc import downrange
 from myhdl._util import _flatten
 from myhdl._ShadowSignal import _TristateSignal, _TristateDriver
 from myhdl._block import _Block
@@ -990,7 +990,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
                       isinstance(node.value.value.obj, _Rom):
             rom = node.value.value.obj.rom
             self.write("case ")
-            if ispythonversion(3, 9) >= 0:
+            if sys.version_info >= (3, 9, 0):  # Python 3.9+: no ast.Index wrapper
                 self.visit(node.value)
             else:
                 self.visit(node.value.slice)
@@ -1586,7 +1586,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
         self.visit(node.value)
         self.write("(")
         # assert len(node.subs) == 1
-        if ispythonversion(3, 9) >= 0:
+        if sys.version_info >= (3, 9, 0):  # Python 3.9+: no ast.Index wrapper
             self.visit(node.slice)
         else:
             self.visit(node.slice.value)
@@ -2397,7 +2397,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
     def accessIndex(self, node):
         self.generic_visit(node)
         node.vhd = vhd_std_logic()  # XXX default
-        if ispythonversion(3, 9) >= 0:
+        if sys.version_info >= (3, 9, 0):  # Python 3.9+: no ast.Index wrapper
             node.slice.vhd = vhd_int()
         else:
             node.slice.value.vhd = vhd_int()
diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
index 015fc696..2f9564df 100644
--- a/myhdl/conversion/_toVerilog.py
+++ b/myhdl/conversion/_toVerilog.py
@@ -16,7 +16,6 @@
 #  You should have received a copy of the GNU Lesser General Public
 #  License along with this library; if not, write to the Free Software
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-from myhdl._misc import ispythonversion
 
 """ myhdl toVerilog conversion module.
 
@@ -759,7 +758,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
 #            self.write("// synthesis parallel_case full_case")
 #            self.writeline()
             self.write("case (")
-            if ispythonversion(3, 9) >= 0:
+            if sys.version_info >= (3, 9, 0):  # Python 3.9+: no ast.Index wrapper
                 self.visit(node.value)
             else:
                 self.visit(node.value.slice)
@@ -1109,6 +1108,8 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
                 s = "1'b%s" % int(obj)
             elif isinstance(obj, int):
                 s = self.IntRepr(obj)
+            elif isinstance(obj, tuple):  # Python3.9+ ast.Index serves a tuple
+                s = str(obj[0])
             elif isinstance(obj, _Signal):
                 addSignBit = isMixedExpr
                 s = str(obj)
@@ -1246,7 +1247,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
         self.visit(node.value)
         self.write("[")
         # assert len(node.subs) == 1
-        if ispythonversion(3, 9) >= 0:
+        if sys.version_info >= (3, 9, 0):  # Python 3.9+: no ast.Index wrapper
             self.visit(node.slice)
         else:
             self.visit(node.slice.value)