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rename for consistency

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This commit is contained in:
Jan Decaluwe 2013-09-14 09:33:42 +02:00
parent 95e103960d
commit 63b4767a3d
1 changed files with 1 additions and 1 deletions
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myhdl/test/bugs/test_enum_toVHDL.py → myhdl/test/bugs/test_bug_enum_toVHDL.py
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@ -26,6 +26,6 @@ next_state_en = Signal(bool(0)) # Enable transition to next state
interrupt_pending = Signal(bool(0))
interrupt_assert = Signal(bool(0))
def test_enum_toVHDL():
def test_bug_enum_toVHDL():
toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert)