added

example/manual/ram.py

@@ -0,0 +1,27 @@
+from myhdl import *
+
+def ram(dout, din, addr, we, clk, depth=128):
+    """  Ram model """
+    
+    mem = [Signal(intbv(0)[8:]) for i in range(depth)]
+    
+    @always(clk.posedge)
+    def write():
+        if we:
+            mem[int(addr)].next = din
+                
+    @always_comb
+    def read():
+        dout.next = mem[int(addr)]
+
+    return write, read
+
+
+dout = Signal(intbv(0)[8:])
+dout_v = Signal(intbv(0)[8:])
+din = Signal(intbv(0)[8:])
+addr = Signal(intbv(0)[7:])
+we = Signal(bool(0))
+clk = Signal(bool(0))
+
+toVerilog(ram, dout, din, addr, we, clk)

example/manual/rom.py

@@ -0,0 +1,19 @@
+from myhdl import *
+
+CONTENT = (17, 134, 52, 9)
+
+def rom(dout, addr, CONTENT):
+    """ ROM model """
+
+    @always_comb
+    def read():
+        dout.next = CONTENT[int(addr)]
+
+    return read
+
+dout = Signal(intbv(0)[8:])
+addr = Signal(intbv(0)[4:])
+CONTENT = (17, 134, 52, 9)
+
+toVerilog(rom, dout, addr, CONTENT)
+