From 65b3295cb46d90afdb4d608e3dda4599c299f923 Mon Sep 17 00:00:00 2001
From: Jan Decaluwe <jan@jandecaluwe.com>
Date: Wed, 10 Sep 2008 17:26:59 +0200
Subject: [PATCH] Support for list of signals in the sensitivity list of simple
 @instance blocks.

---
 myhdl/conversion/_analyze.py                  |  8 ++--
 myhdl/conversion/_toVerilog.py                |  7 ++-
 .../conversion/general/test_listofsigs.py     | 46 ++++++++++++++++---
 3 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py
index 1b70f742..c7153e90 100644
--- a/myhdl/conversion/_analyze.py
+++ b/myhdl/conversion/_analyze.py
@@ -873,10 +873,12 @@ class _AnalyzeVisitor(_ConversionMixin):
                 if not isinstance(n.obj, (Signal, _WaiterList)):
                     self.raiseError(node, _error.UnsupportedYield)
                 senslist.append(n.obj)
-        else:
-            if not isinstance(n.obj, (Signal, _WaiterList, delay)):
-                self.raiseError(node, _error.UnsupportedYield)
+        elif isinstance(n.obj, (Signal, _WaiterList, delay)):
             senslist = [n.obj]
+        elif _isMem(n.obj):
+            senslist = n.obj
+        else:
+            self.raiseError(node, _error.UnsupportedYield)
         node.senslist = senslist
 
 ##     def visitModule(self, node, *args):
diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
index 572bbae4..f5d013d7 100644
--- a/myhdl/conversion/_toVerilog.py
+++ b/myhdl/conversion/_toVerilog.py
@@ -1028,8 +1028,13 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
             y = y.expr
         assert isinstance(y, astNode.Yield)
         sl = y.value
+        assert y.senslist
+        self.ast.senslist = y.senslist
         self.write("always @(")
-        self.visit(sl, _context.YIELD)
+        for e in self.ast.senslist[:-1]:
+            self.write(e._toVerilog())
+            self.write(', ')
+        self.write(self.ast.senslist[-1]._toVerilog())
         self.write(") begin: %s" % self.ast.name)
         self.indent()
         self.writeDeclarations()
diff --git a/myhdl/test/conversion/general/test_listofsigs.py b/myhdl/test/conversion/general/test_listofsigs.py
index b5180ddf..ed303069 100644
--- a/myhdl/test/conversion/general/test_listofsigs.py
+++ b/myhdl/test/conversion/general/test_listofsigs.py
@@ -1,13 +1,14 @@
 from myhdl import *
 
+N = 8
+M= 2**N
+
 
 ### A first case that already worked with 5.0 list of signal constraints ###
 
 def intbv2list():
     """Conversion between intbv and list of boolean signals."""
     
-    N = 8
-    M= 2**N
     a = Signal(intbv(0)[N:])
     b = [Signal(bool(0)) for i in range(len(a))]
     z = Signal(intbv(0)[N:])
@@ -47,6 +48,7 @@ def inv1(z, a):
         z.next = not a
     return logic
 
+
 def inv2(z, a):
     @always_comb
     def logic():
@@ -54,6 +56,15 @@ def inv2(z, a):
     return logic
 
 
+def inv3(z, a):
+    @instance
+    def logic():
+        while True:
+            yield a
+            z.next = not a
+    return logic
+
+
 def case1(z, a, inv):
     b = [Signal(bool(1)) for i in range(len(a))]
     c = [Signal(bool(0)) for i in range(len(a))]
@@ -73,6 +84,7 @@ def case1(z, a, inv):
 
     return extract, inst, assemble
 
+
 def case2(z, a, inv):
     b = [Signal(bool(1)) for i in range(len(a))]
     c = [Signal(bool(0)) for i in range(len(a))]
@@ -93,15 +105,34 @@ def case2(z, a, inv):
     return extract, inst, assemble
 
 
+def case3(z, a, inv):
+    b = [Signal(bool(1)) for i in range(len(a))]
+    c = [Signal(bool(0)) for i in range(len(a))]
+    @instance
+    def extract():
+        while True:
+            yield a
+            for i in range(len(a)):
+                b[i].next = a[i]
+
+    inst = [None] * len(b)
+    for i in range(len(b)):
+        inst[i] = inv(c[i], b[i])
+
+    @instance
+    def assemble():
+        while True:
+            yield c
+            for i in range(len(c)):
+                z.next[i] = c[i]
+
+    return extract, inst, assemble
+
 
 def processlist(case, inv):
     """Extract list from intbv, do some processing, reassemble."""
     
-    N = 8
-    M = 2**N
     a = Signal(intbv(1)[N:])
-    b = [Signal(bool(1)) for i in range(len(a))]
-    c = [Signal(bool(0)) for i in range(len(a))]
     z = Signal(intbv(0)[N:])
 
     case_inst = case(z, a, inv)
@@ -129,6 +160,9 @@ def test_processlist12():
     
 def test_processlist22():
     assert conversion.verify(processlist, case2, inv2) == 0
+    
+def test_processlist33():
+    assert conversion.verify(processlist, case3, inv3) == 0