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Finally?
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@ -969,7 +969,6 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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self.generic_visit(node)
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def visit_Subscript(self, node):
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print('Analyze', node.slice)
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if isinstance(node.slice, ast.Slice):
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self.accessSlice(node)
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else:
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@ -990,10 +990,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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isinstance(node.value.value.obj, _Rom):
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rom = node.value.value.obj.rom
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self.write("case ")
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if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
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self.visit(node.value)
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else:
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self.visit(node.value.slice)
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self.visit(node.value.slice)
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self.write(" is")
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self.indent()
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size = lhs.vhd.size
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@ -1195,7 +1192,15 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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if isinstance(node.value, int):
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if node.value is None:
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# NameConstant
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node.id = str(node.value)
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self.getName(node)
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elif isinstance(node.value, bool):
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# NameConstant
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node.id = str(node.value)
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self.getName(node)
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elif isinstance(node.value, int):
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# Num
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n = node.value
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if isinstance(node.vhd, vhd_std_logic):
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@ -1220,10 +1225,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.write(n)
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if n < 0:
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self.write(")")
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elif node.value in (True, False, None):
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# NameConstant
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node.id = str(node.value)
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self.getName(node)
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elif isinstance(node.value, str):
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# Str
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typemark = 'string'
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@ -1515,7 +1516,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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else:
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s = 'signed\'("%s")' % tobin(obj, node.vhd.size)
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elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple
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print('toVHDL: getName:', node, n, obj)
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s = n
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elif isinstance(obj, _Signal):
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s = str(obj)
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@ -2297,15 +2297,18 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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if isinstance(node.value, int):
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if node.value is None:
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# NameConstant
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node.vhd = inferVhdlObj(node.value)
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elif isinstance(node.value, bool):
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# NameConstant
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node.vhd = inferVhdlObj(node.value)
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elif isinstance(node.value, int):
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# Num
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if node.value < 0:
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node.vhd = vhd_int()
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else:
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node.vhd = vhd_nat()
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elif node.value in (True, False, None):
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# NameConstant
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node.vhd = inferVhdlObj(node.value)
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elif isinstance(node.value, str):
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# Str
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node.vhd = vhd_string()
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@ -856,7 +856,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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elif f is concat:
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opening, closing = '{', '}'
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elif f is delay:
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print('toVerilog: visit_Call:', node, node.args[0])
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self.visit(node.args[0])
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return
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elif hasattr(node, 'tree'):
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@ -892,7 +891,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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if sys.version_info >= (3, 9, 0):
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def visit_Constant(self, node):
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print('toVerilog: visit_Constant:', node.value, end=': ')
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if node.value is None:
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# NameConstant
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print('NameConstant: None')
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@ -1138,11 +1136,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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elif isinstance(obj, int):
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s = self.IntRepr(obj)
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elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple
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print('toVerilog: getName:', node, addSignBit, n, obj)
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s = n
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# # print(ast.dump(ast.parse('l[i]', mode='eval')))
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# # Expression(body=Subscript(value=Name(id='l', ctx=Load()), slice=Index(value=Name(id='i', ctx=Load())), ctx=Load()))
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elif isinstance(obj, _Signal):
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addSignBit = isMixedExpr
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s = str(obj)
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@ -1281,7 +1275,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.write("[")
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# assert len(node.subs) == 1
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if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
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print('toVerilog: accessIndex:', node, node.slice)
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self.visit(node.slice)
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else:
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self.visit(node.slice.value)
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@ -1335,7 +1328,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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if isinstance(yieldObj, delay):
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self.write("# ")
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self.context = _context.YIELD
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print('toVerilog: visit_Yield: delay:', node, node.value)
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self.visit(node.value)
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self.context = _context.UNKNOWN
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self.write(";")
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