From 65c456b6809ba33b933a396d8dc05b5777b50b33 Mon Sep 17 00:00:00 2001 From: Josy Boelen Date: Sun, 7 Mar 2021 14:13:30 +0100 Subject: [PATCH] Finally? --- myhdl/conversion/_analyze.py | 1 - myhdl/conversion/_toVHDL.py | 31 +++++++++++++++++-------------- myhdl/conversion/_toVerilog.py | 8 -------- 3 files changed, 17 insertions(+), 23 deletions(-) diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index e90a319f..35af88ca 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -969,7 +969,6 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): self.generic_visit(node) def visit_Subscript(self, node): - print('Analyze', node.slice) if isinstance(node.slice, ast.Slice): self.accessSlice(node) else: diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 263ecd9b..19f5b881 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -990,10 +990,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): isinstance(node.value.value.obj, _Rom): rom = node.value.value.obj.rom self.write("case ") - if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper - self.visit(node.value) - else: - self.visit(node.value.slice) + self.visit(node.value.slice) self.write(" is") self.indent() size = lhs.vhd.size @@ -1195,7 +1192,15 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): if sys.version_info >= (3, 9, 0): def visit_Constant(self, node): - if isinstance(node.value, int): + if node.value is None: + # NameConstant + node.id = str(node.value) + self.getName(node) + elif isinstance(node.value, bool): + # NameConstant + node.id = str(node.value) + self.getName(node) + elif isinstance(node.value, int): # Num n = node.value if isinstance(node.vhd, vhd_std_logic): @@ -1220,10 +1225,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): self.write(n) if n < 0: self.write(")") - elif node.value in (True, False, None): - # NameConstant - node.id = str(node.value) - self.getName(node) elif isinstance(node.value, str): # Str typemark = 'string' @@ -1515,7 +1516,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): else: s = 'signed\'("%s")' % tobin(obj, node.vhd.size) elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple - print('toVHDL: getName:', node, n, obj) s = n elif isinstance(obj, _Signal): s = str(obj) @@ -2297,15 +2297,18 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin): if sys.version_info >= (3, 9, 0): def visit_Constant(self, node): - if isinstance(node.value, int): + if node.value is None: + # NameConstant + node.vhd = inferVhdlObj(node.value) + elif isinstance(node.value, bool): + # NameConstant + node.vhd = inferVhdlObj(node.value) + elif isinstance(node.value, int): # Num if node.value < 0: node.vhd = vhd_int() else: node.vhd = vhd_nat() - elif node.value in (True, False, None): - # NameConstant - node.vhd = inferVhdlObj(node.value) elif isinstance(node.value, str): # Str node.vhd = vhd_string() diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index c59e4ed2..628eb6b8 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -856,7 +856,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): elif f is concat: opening, closing = '{', '}' elif f is delay: - print('toVerilog: visit_Call:', node, node.args[0]) self.visit(node.args[0]) return elif hasattr(node, 'tree'): @@ -892,7 +891,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): if sys.version_info >= (3, 9, 0): def visit_Constant(self, node): - print('toVerilog: visit_Constant:', node.value, end=': ') if node.value is None: # NameConstant print('NameConstant: None') @@ -1138,11 +1136,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): elif isinstance(obj, int): s = self.IntRepr(obj) elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple - print('toVerilog: getName:', node, addSignBit, n, obj) s = n -# # print(ast.dump(ast.parse('l[i]', mode='eval'))) -# # Expression(body=Subscript(value=Name(id='l', ctx=Load()), slice=Index(value=Name(id='i', ctx=Load())), ctx=Load())) - elif isinstance(obj, _Signal): addSignBit = isMixedExpr s = str(obj) @@ -1281,7 +1275,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): self.write("[") # assert len(node.subs) == 1 if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper - print('toVerilog: accessIndex:', node, node.slice) self.visit(node.slice) else: self.visit(node.slice.value) @@ -1335,7 +1328,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin): if isinstance(yieldObj, delay): self.write("# ") self.context = _context.YIELD - print('toVerilog: visit_Yield: delay:', node, node.value) self.visit(node.value) self.context = _context.UNKNOWN self.write(";")