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# This file is part of the myhdl library, a Python package for using
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# Python as a Hardware Description Language.
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#
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# Copyright (C) 2003 Jan Decaluwe
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#
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# The myhdl library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public License as
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# published by the Free Software Foundation; either version 2.1 of the
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# License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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""" myhdl trace_sigs module.
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"""
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__author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
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__revision__ = "$Revision$"
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__date__ = "$Date$"
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from __future__ import generators
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import sys
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from inspect import currentframe, getframeinfo, getouterframes
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import compiler
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import re
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import string
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import time
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from types import FunctionType
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import os
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path = os.path
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import shutil
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from myhdl import _simulator, Signal, __version__
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from myhdl._util import _isGenSeq, _isgeneratorfunction
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_tracing = 0
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class Error(Exception):
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""" trace_sigs Error"""
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def __init__(self, arg=""):
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self.arg = arg
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def __str__(self):
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msg = self.__doc__
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if self.arg:
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msg = msg + ": " + str(self.arg)
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return msg
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class TopLevelNameError(Error):
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"""result of trace_sigs call should be assigned to a top level name"""
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class ArgTypeError(Error):
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"""trace_sigs first argument should be a classic function"""
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class NoInstancesError(Error):
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"""trace_sigs returned no instances"""
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re_assign = r"""^
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\s*
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(?P<name>\w[\w\d]*)
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(?P<index>\[.*\])?
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\s*
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=
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"""
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rex_assign = re.compile(re_assign, re.X)
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def trace_sigs(dut, *args, **kwargs):
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global _tracing
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if _tracing:
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return dut(*args, **kwargs) # skip
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if not callable(dut):
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raise ArgTypeError("got %s" % type(dut))
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if _isgeneratorfunction(dut):
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raise ArgTypeError("got generator function")
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_tracing = 1
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try:
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outer = getouterframes(currentframe())[1]
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name = _findInstanceName(outer)
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if name is None:
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raise TopLevelNameError
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h = _HierExtr(name, dut, *args, **kwargs)
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vcdpath = name + ".vcd"
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if path.exists(vcdpath):
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backup = vcdpath + '.' + str(path.getmtime(vcdpath))
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shutil.copyfile(vcdpath, backup)
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os.remove(vcdpath)
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vcdfile = open(vcdpath, 'w')
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_simulator._tracing = 1
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_simulator._tf = vcdfile
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_writeVcdHeader(vcdfile)
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_writeVcdSigs(vcdfile, h.instances)
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finally:
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_tracing = 0
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return h.m
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def _findInstanceName(framerec):
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f = framerec[0]
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c = framerec[4][0]
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m = rex_assign.match(c)
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name = None
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if m:
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basename, index = m.groups()
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if index:
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il = []
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for i in index[1:-1].split("]["):
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try:
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s = str(eval(i, f.f_globals, f.f_locals))
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except:
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break
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il.append(s)
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else:
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name = basename + '[' + "][".join(il) + ']'
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else:
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name = basename
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return name
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class _HierExtr(object):
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def __init__(self, name, dut, *args, **kwargs):
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self.names = [name]
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self.instances = instances = []
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self.level = 0
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sys.setprofile(self.extractor)
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try:
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_top = dut(*args, **kwargs)
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finally:
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sys.setprofile(None)
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if not instances:
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raise NoInstancesError
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self.m = _top
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instances.reverse()
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instances[0][1] = name
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def extractor(self, frame, event, arg):
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if event == "call":
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outer = getouterframes(frame)[1]
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name = _findInstanceName(outer)
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self.names.append(name)
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if name:
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self.level += 1
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elif event == "return":
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name = self.names.pop()
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if name:
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if _isGenSeq(arg):
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sigdict = {}
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for dict in (frame.f_locals, frame.f_globals):
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for n, v in dict.items():
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if isinstance(v, Signal):
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sigdict[n] = v
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i = [self.level, name, sigdict]
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self.instances.append(i)
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self.level -= 1
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_codechars = ""
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for i in range(33, 127):
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_codechars += chr(i)
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_mod = len(_codechars)
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def _genNameCode():
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n = 0
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while 1:
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yield _namecode(n)
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n += 1
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def _namecode(n):
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q, r = divmod(n, _mod)
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code = _codechars[r]
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while q > 0:
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q, r = divmod(q, _mod)
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code = _codechars[r] + code
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return code
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def _writeVcdHeader(f):
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print >> f, "$date"
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print >> f, " %s" % time.asctime()
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print >> f, "$end"
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print >> f, "$version"
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print >> f, " MyHDL %s" % __version__
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print >> f, "$end"
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print >> f, "$timesscale"
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print >> f, " 1ns"
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print >> f, "$end"
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print >> f
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def _writeVcdSigs(f, instances):
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curlevel = 0
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namegen = _genNameCode()
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siglist = []
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for level, name, sigdict in instances:
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delta = curlevel - level
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curlevel = level
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assert(delta >= -1)
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if delta >= 0:
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for i in range(delta + 1):
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print >> f, "$upscope $end"
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print >> f, "$scope module %s $end" % name
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for n, s in sigdict.items():
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if not s._tracing:
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s._tracing = 1
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s._code = namegen.next()
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siglist.append(s)
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w = s._nrbits
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if w:
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if w == 1:
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print >> f, "$var reg 1 %s %s $end" % (s._code, n)
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else:
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print >> f, "$var reg %s %s %s $end" % (w, s.code, n)
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else:
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print >> f, "$var real 1 %s %s $end" % (s._code, n)
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for i in range(curlevel):
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print >> f, "$upscope $end"
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print >> f
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print >> f, "$enddefinitions $end"
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print >> f, "$dumpvars"
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for s in siglist:
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s._printVcd() # initial value
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print >> f, "$end"
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@ -1,162 +0,0 @@
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# This file is part of the myhdl library, a Python package for using
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# Python as a Hardware Description Language.
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#
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# Copyright (C) 2003 Jan Decaluwe
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#
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# The myhdl library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public License as
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# published by the Free Software Foundation; either version 2.1 of the
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# License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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""" Run the unit tests for bin """
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__author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
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__revision__ = "$Revision$"
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__date__ = "$Date$"
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from __future__ import generators
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import random
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from random import randrange
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random.seed(1) # random, but deterministic
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import sys
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import os
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path = os.path
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import unittest
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from unittest import TestCase
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import shutil
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from myhdl import delay, Signal, Simulation
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from myhdl._trace_sigs import trace_sigs, TopLevelNameError, ArgTypeError, \
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NoInstancesError
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QUIET=1
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def gen(clk):
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while 1:
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yield delay(10)
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clk.next = not clk
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def fun():
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clk = Signal(bool(0))
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inst = gen(clk)
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return inst
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def dummy():
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clk = Signal(bool(0))
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inst = gen(clk)
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return 1
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def top():
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inst = trace_sigs(fun)
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return inst
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def top2():
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inst = [{} for i in range(4)]
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j = 3
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inst[j-2]['key'] = trace_sigs(fun)
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return inst
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class TestTraceSigs(TestCase):
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def setUp(self):
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self.paths = paths = ["dut.vcd", "inst.vcd"]
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for p in paths:
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if path.exists(p):
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os.remove(p)
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def tearDown(self):
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for p in self.paths:
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if path.exists(p):
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os.remove(p)
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def testTopName(self):
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p = "dut.vcd"
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dut = trace_sigs(fun)
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try:
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trace_sigs(fun)
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except TopLevelNameError:
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pass
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else:
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self.fail()
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def testArgType1(self):
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p = "dut.vcd"
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try:
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dut = trace_sigs([1, 2])
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except ArgTypeError:
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pass
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else:
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self.fail()
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def testArgType2(self):
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p = "dut.vcd"
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try:
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dut = trace_sigs(gen, Signal(0))
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except ArgTypeError:
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pass
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else:
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self.fail()
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def testReturnVal(self):
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p = "dut.vcd"
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try:
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dut = trace_sigs(dummy)
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except NoInstancesError:
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pass
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else:
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self.fail()
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def testHierarchicalTrace1(self):
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p = "inst.vcd"
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top()
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self.assert_(path.exists(p))
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def testHierarchicalTrace2(self):
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pdut = "dut.vcd"
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psub = "inst.vcd"
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dut = trace_sigs(top)
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self.assert_(path.exists(pdut))
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self.assert_(not path.exists(psub))
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def testIndexedName(self):
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p = "dut[1][0].vcd"
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dut = [[None] * 3 for i in range(4)]
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i, j = 0, 2
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dut[i+1][j-2] = trace_sigs(top)
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self.assert_(path.exists(p))
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os.remove(p)
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def testIndexedName2(self):
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p = "inst[1][key].vcd"
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top2()
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self.assert_(path.exists(p))
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os.remove(p)
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def testBackupOutputFile(self):
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p = "dut.vcd"
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dut = trace_sigs(fun)
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Simulation(dut).run(1000, quiet=QUIET)
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size = path.getsize(p)
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pbak = p + '.' + str(path.getmtime(p))
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self.assert_(not path.exists(pbak))
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dut = trace_sigs(fun)
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self.assert_(path.exists(p))
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self.assert_(path.exists(pbak))
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self.assert_(path.getsize(pbak) == size)
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self.assert_(path.getsize(p) < size)
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os.remove(pbak)
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if __name__ == "__main__":
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unittest.main()
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