added nested interface to the interface test

myhdl/conversion/_verify.py

@@ -69,7 +69,7 @@ registerSimulator(
 registerSimulator(
     name="vcom",
     hdl="VHDL",
-    analyze="vcom -work work_vcom pck_myhdl_%(version)s.vhd %(topname)s.vhd",
+    analyze="vcom -2008 -work work_vcom pck_myhdl_%(version)s.vhd %(topname)s.vhd",
     simulate='vsim work_vcom.%(topname)s -quiet -c -do "run -all; quit -f"',
     skiplines=6,
     skipchars=2,

myhdl/test/conversion/general/test_interfaces4.py

@@ -1,22 +1,18 @@
-from __future__ import absolute_import
 
 import sys
 
 import myhdl
-from myhdl import *
-from myhdl import ConversionError
-from myhdl.conversion._misc import _error
+from myhdl import (block, Signal, ResetSignal, modbv, always_seq, concat,
+                   instance, delay, StopSimulation)
 from myhdl.conversion import analyze, verify
 
-import myhdl
-from myhdl import *
+"""
+This set of tests exercises a peculiar scenario where an expanded
+interface Signal is flagged as having multiple drivers.  This appears
+to be a name collision in the name expansion and was introduced in
+08519b4.
+"""
 
-"""
-This set of tests exercies a peculiar scenario where an
-expanded interface Signal is flagged as having multiple
-drivers.  This appears to be a name collision in the name
-expansion and was introduced in 08519b4.  
-"""
 
 class Intf1(object):
     def __init__(self):
@@ -32,11 +28,13 @@ class Intf2(object):
         self.sig3 = Signal(modbv(0)[8:])
         self.intf = Intf1()
 
+
 @block
-def mod1(clock, reset, intf1, intf2):
+def use_nested_intf(clock, reset, intf1, intf2):
     
     sig1 = Signal(bool(0))
     sig2 = Signal(bool(0))
+
     @always_seq(clock.posedge, reset)
     def proc():
         if intf1.sig1:
@@ -49,12 +47,15 @@ def mod1(clock, reset, intf1, intf2):
         intf2.sig1.next = sig1
         intf2.sig2.next = sig2 or intf1.sig2
         intf2.sig3.next = ~intf1.sig3
+        intf2.intf.sig1.next = intf2.sig2
+        intf2.intf.sig2.next = intf2.intf.sig1
 
     return proc
 
 
 @block
-def mod2(clock, reset, intf1, intf2):
+def something_peculiar(clock, reset, intf1, intf2):
+
     @always_seq(clock.posedge, reset)
     def proc():
         # remove the if/else and leave just the line in the
@@ -71,14 +72,12 @@ def mod2(clock, reset, intf1, intf2):
 
 
 @block
-def m_top(clock, reset, sdi, sdo):
+def interfaces_top(clock, reset, sdi, sdo, nested):
     
-    intf1 = Intf1()
-    intf2 = Intf2()
-    intf3 = Intf1()
+    intf1, intf2, intf3 = Intf1(), Intf2(), Intf1()
 
-    g1 = mod1(clock, reset, intf1, intf2)
-    g2 = mod2(clock, reset, intf2, intf3)
+    inst1 = use_nested_intf(clock, reset, intf1, intf2)
+    inst2 = something_peculiar(clock, reset, intf2, intf3)
 
     @always_seq(clock.posedge, reset)
     def assigns():
@@ -86,8 +85,9 @@ def m_top(clock, reset, sdi, sdo):
         intf1.sig2.next = not sdi
         intf1.sig3.next = concat(intf1.sig3[7:1], sdi)
         sdo.next = intf3.sig1 | intf3.sig2 | intf3.sig3[2]
+        nested.next = intf2.intf.sig2
 
-    return g1, g2, assigns
+    return inst1, inst2, assigns
 
 
 @block
@@ -101,7 +101,8 @@ def c_testbench_one():
     reset = ResetSignal(0, active=1, async=False)
     sdi = Signal(bool(0))
     sdo = Signal(bool(0))
-    tbdut = m_top(clock, reset, sdi, sdo)
+    nested = Signal(bool())
+    tbdut = interfaces_top(clock, reset, sdi, sdo, nested)
 
     @instance    
     def tbclk():
@@ -110,13 +111,14 @@ def c_testbench_one():
             yield delay(3)
             clock.next = not clock
      
-    # there is an issue when using bools with varialbes and
+    # there is an issue when using bools with variables and
     # VHDL conversion, this might be an expected limitation?
-    #expected = (False, False, False, True, True, True,
+    # expected = (False, False, False, True, True, True,
     #             False, True, False, True)
+    # use a tuple-of-ints instead of the above tuple-of-bools
     expected = (0, 0, 0, 1, 1, 1, 0, 1, 0, 1)
-
     ra = reset.active
+
     @instance
     def tbstim():
         sdi.next = False
@@ -125,7 +127,7 @@ def c_testbench_one():
         reset.next = not ra
         yield clock.posedge
         for ii in range(10):
-            print("sdi: %d, sdo: %d" % (sdi, sdo))
+            print("sdi: %d, sdo: %d, nested: %d" % (sdi, sdo, nested))
             expected_bit = expected[ii]
             assert sdo == expected_bit
             sdi.next = not sdi
@@ -137,11 +139,8 @@ def c_testbench_one():
 
 
 def test_one_testbench():
-    clock = Signal(bool(0))
-    reset = ResetSignal(0, active=1, async=False)
-    sdi = Signal(bool(0))
-    sdo = Signal(bool(0))
-    Simulation(c_testbench_one()).run()
+    inst = c_testbench_one()
+    inst.run_sim()
 
 
 def test_one_analyze():
@@ -149,7 +148,8 @@ def test_one_analyze():
     reset = ResetSignal(0, active=1, async=False)
     sdi = Signal(bool(0))
     sdo = Signal(bool(0))
-    analyze(m_top(clock, reset, sdi, sdo))
+    nested = Signal(bool(0))
+    assert analyze(interfaces_top(clock, reset, sdi, sdo, nested)) == 0
 
 
 def test_one_verify():
@@ -157,19 +157,6 @@ def test_one_verify():
 
 
 def test_conversion():
-    toVerilog(c_testbench_one())
-    toVHDL(c_testbench_one())
-
-
-if __name__ == '__main__':
-    print(sys.argv[1])
-    verify.simulator = analyze.simulator = sys.argv[1]
-    print("*** verify example testbench ")
-    test_one_testbench()
-    print("*** verify example module conversion ")
-    test_one_analyze()
-    print("*** test testbench conversion ")
-    test_conversion()
-    print("*** verify testbench conversion and execution")
-    test_one_verify()
-    
+    inst = c_testbench_one()
+    inst.convert(hdl='Verilog')
+    inst.convert(hdl='VHDL')