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Merge pull request #11 from jck/master

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conv: allow modifying bits of signals inside lists
This commit is contained in:
jandecaluwe 2015-02-27 08:44:51 +01:00
commit 69c89fa70e
2 changed files with 8 additions and 0 deletions
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4
myhdl/conversion/_toVHDL.py
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@ -776,6 +776,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
node.obj = self.getObj(node.value)
def getAttr(self, node):
if isinstance(node.value, ast.Subscript):
self.setAttr(node)
return
assert isinstance(node.value, ast.Name), node.value
n = node.value.id
if n in self.tree.symdict:

4
myhdl/conversion/_toVerilog.py
View File

@ -603,6 +603,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.visit(node.value)
def getAttr(self, node):
if isinstance(node.value, ast.Subscript):
self.setAttr(node)
return
assert isinstance(node.value, ast.Name), node.value
n = node.value.id
if n in self.tree.symdict: