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generalized shadow signal, created _SliceSignal subclass

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This commit is contained in:
Jan Decaluwe 2009-06-09 18:33:55 +02:00
parent cab4c4be8b
commit 6a280b0767
3 changed files with 27 additions and 11 deletions
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28
myhdl/_Signal.py
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@ -277,7 +277,7 @@ class _Signal(object):
### use call interface for shadow signals ###
def __call__(self, left, right=None):
return _ShadowSignal(self, left, right)
return _SliceSignal(self, left, right)
### operators for which delegation to current value is appropriate ###
@ -532,8 +532,20 @@ class _SignalWrap(object):
return self.sig._apply(self.next, self.timeStamp)
# shadow signals
class _ShadowSignal(_Signal):
__slots__ = ('gen', )
class _SliceSignal(_ShadowSignal):
__slots__ = ('sig', 'left', 'right')
def __init__(self, sig, left, right=None):
### XXX error checks
if right is None:
@ -562,5 +574,15 @@ class _ShadowSignal(_Signal):
while 1:
set_next(self, sig[left:right])
yield sig
def toVerilog(self):
if self.right is None:
return "assign %s = %s[%s];" % (self._name, self.sig._name, self.left)
else:
return "assign %s = %s[%s-1:%s];" % (self._name, self.sig._name, self.left, self.right)
def toVHDL(self):
if self.right is None:
return "%s <= %s(%s);" % (self._name, self.sig._name, self.left)
else:
return "%s <= %s(%s-1 downto %s);" % (self._name, self.sig._name, self.left, self.right)

5
myhdl/conversion/_toVHDL.py
View File

@ -353,10 +353,7 @@ def _convertGens(genlist, siglist, vfile):
for s in siglist:
if not isinstance(s, _ShadowSignal):
continue
if s.right is None:
print >> vfile, "%s <= %s(%s);" % (s._name, s.sig._name, s.left)
else:
print >> vfile, "%s <= %s(%s-1 downto %s);" % (s._name, s.sig._name, s.left, s.right)
print >> vfile, s.toVHDL()
print >> vfile
vfile.write(blockBuf.getvalue()); blockBuf.close()

5
myhdl/conversion/_toVerilog.py
View File

@ -241,10 +241,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
for s in siglist:
if not isinstance(s, _ShadowSignal):
continue
if s.right is None:
print >> f, "assign %s = %s[%s];" % (s._name, s.sig._name, s.left)
else:
print >> f, "assign %s = %s[%s-1:%s];" % (s._name, s.sig._name, s.left, s.right)
print >> f, s.toVerilog()
print >> f