From 6a280b07673ca52aff25819c42a33e1a1fa551b5 Mon Sep 17 00:00:00 2001
From: Jan Decaluwe <jan@jandecaluwe.com>
Date: Tue, 9 Jun 2009 18:33:55 +0200
Subject: [PATCH] generalized shadow signal, created _SliceSignal subclass

---
 myhdl/_Signal.py               | 28 +++++++++++++++++++++++++---
 myhdl/conversion/_toVHDL.py    |  5 +----
 myhdl/conversion/_toVerilog.py |  5 +----
 3 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
index cc09a759..51909ff8 100644
--- a/myhdl/_Signal.py
+++ b/myhdl/_Signal.py
@@ -277,7 +277,7 @@ class _Signal(object):
 
     ### use call interface for shadow signals ###
     def __call__(self, left, right=None):
-        return _ShadowSignal(self, left, right)
+        return _SliceSignal(self, left, right)
 
     ### operators for which delegation to current value is appropriate ###
         
@@ -532,8 +532,20 @@ class _SignalWrap(object):
         return self.sig._apply(self.next, self.timeStamp)
 
 
+
+# shadow signals
+        
+        
 class _ShadowSignal(_Signal):
 
+    __slots__ = ('gen', )
+
+
+        
+class _SliceSignal(_ShadowSignal):
+
+    __slots__ = ('sig', 'left', 'right')
+
     def __init__(self, sig, left, right=None):
         ### XXX error checks
         if right is None:
@@ -562,5 +574,15 @@ class _ShadowSignal(_Signal):
         while 1:
             set_next(self, sig[left:right])
             yield sig
-        
-        
+
+    def toVerilog(self):
+        if self.right is None:
+            return "assign %s = %s[%s];" % (self._name, self.sig._name, self.left)
+        else:
+            return "assign %s = %s[%s-1:%s];" % (self._name, self.sig._name, self.left, self.right)
+
+    def toVHDL(self):
+        if self.right is None:
+            return "%s <= %s(%s);" % (self._name, self.sig._name, self.left)
+        else:
+            return "%s <= %s(%s-1 downto %s);" % (self._name, self.sig._name, self.left, self.right)
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index 949e401f..150d28b0 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -353,10 +353,7 @@ def _convertGens(genlist, siglist, vfile):
     for s in siglist:
         if not isinstance(s, _ShadowSignal):
             continue
-        if s.right is None:
-            print >> vfile, "%s <= %s(%s);" % (s._name, s.sig._name, s.left)
-        else:
-            print >> vfile, "%s <= %s(%s-1 downto %s);" % (s._name, s.sig._name, s.left, s.right)
+        print >> vfile, s.toVHDL()
     print >> vfile
 
     vfile.write(blockBuf.getvalue()); blockBuf.close()
diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
index 6bb1b6f3..35fab35e 100644
--- a/myhdl/conversion/_toVerilog.py
+++ b/myhdl/conversion/_toVerilog.py
@@ -241,10 +241,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
     for s in siglist:
         if not isinstance(s, _ShadowSignal):
             continue
-        if s.right is None:
-            print >> f, "assign %s = %s[%s];" % (s._name, s.sig._name, s.left)
-        else:
-            print >> f, "assign %s = %s[%s-1:%s];" % (s._name, s.sig._name, s.left, s.right)
+        print >> f, s.toVerilog()
     print >> f