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jand 2003-05-16 08:33:46 +00:00
parent 28278e8d35
commit 6c0d327274
1 changed files with 1 additions and 1 deletions
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cosimulation/test/verilog/bin2gray.v
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@ -7,7 +7,7 @@ module bin2gray(B, G);
integer i;
wire [width:0] extB;
assign extB = {1'b0, B};
assign extB = {1'b0, B}; // zero-extend input
always @(extB) begin
for (i=0; i < width; i=i+1)