From 6c0d32727418df8b7575934e72c5a5cd6b6f6ed9 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Fri, 16 May 2003 08:33:46 +0000
Subject: [PATCH] comment

---
 cosimulation/test/verilog/bin2gray.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cosimulation/test/verilog/bin2gray.v b/cosimulation/test/verilog/bin2gray.v
index f8a46439..c844d5f0 100644
--- a/cosimulation/test/verilog/bin2gray.v
+++ b/cosimulation/test/verilog/bin2gray.v
@@ -7,7 +7,7 @@ module bin2gray(B, G);
    integer i;
    wire [width:0] extB;
 
-   assign extB = {1'b0, B};
+   assign extB = {1'b0, B}; // zero-extend input
 
    always @(extB) begin
       for (i=0; i < width; i=i+1)