1
0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00

Updating uart_tx example to use @block decorator and new API. (#320)

* Updating uart_tx example to use @block decorator and new API.

* Removed wildcard import of myhdl.

* Removed unnecessary import myhdl.
This commit is contained in:
richmorj 2019-09-15 02:15:56 +01:00 committed by Christopher Felton
parent 829f6f94ed
commit 6c25cb252a

View File

@ -1,6 +1,6 @@
import myhdl
from myhdl import *
from myhdl import always, always_seq, block, delay, enum, instance, intbv, ResetSignal, Signal, StopSimulation
@block
def uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst):
index = Signal(intbv(0, min=0, max=8))
@ -31,6 +31,7 @@ def uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst):
return fsm
@block
def uart_tx_2(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst):
index = Signal(intbv(0, min=0, max=8))
@ -57,7 +58,7 @@ def uart_tx_2(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst):
return fsm
@block
def tb(uart_tx):
tx_bit = Signal(bool(1))
@ -95,9 +96,11 @@ def tb(uart_tx):
return clk_gen, stimulus, uart_tx_inst
sim = Simulation(traceSignals(tb, uart_tx_2))
dut = uart_tx_2
inst = tb(dut)
sim.run()
inst.config_sim(trace=True)
inst.run_sim(10000)
@ -108,4 +111,4 @@ sim.run()