FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

object files name suffic .o

Browse Source
This commit is contained in:
jand 2005-10-03 15:49:36 +00:00
parent dd4760d43f
commit 6d292f6e19
5 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
cosimulation/icarus/test/bin2gray.py
View File

@ -2,13 +2,13 @@ import os
from myhdl import Cosimulation
cmd = "iverilog -o bin2gray -Dwidth=%s " + \
cmd = "iverilog -o bin2gray.o -Dwidth=%s " + \
"../../test/verilog/bin2gray.v " + \
"../../test/verilog/dut_bin2gray.v "
def bin2gray(B, G, width):
os.system(cmd % width)
return Cosimulation("vvp -m ../myhdl.vpi bin2gray", B=B, G=G)
return Cosimulation("vvp -m ../myhdl.vpi bin2gray.o", B=B, G=G)

4
cosimulation/icarus/test/dff.py
View File

@ -2,11 +2,11 @@ import os
from myhdl import Cosimulation
cmd = "iverilog -o dff " + \
cmd = "iverilog -o dff.o " + \
"../../test/verilog/dff.v " + \
"../../test/verilog/dut_dff.v "
def dff(q, d, clk, reset):
os.system(cmd)
return Cosimulation("vvp -m ../myhdl.vpi dff", **locals())
return Cosimulation("vvp -m ../myhdl.vpi dff.o", **locals())

4
cosimulation/icarus/test/dff_clkout.py
View File

@ -3,7 +3,7 @@ import os.path as path
from myhdl import Cosimulation
cmd = "iverilog -o dff_clkout " + \
cmd = "iverilog -o dff_clkout.o " + \
"../../test/verilog/dff_clkout.v " + \
"../../test/verilog/dut_dff_clkout.v "
@ -11,5 +11,5 @@ def dff_clkout(clkout, q, d, clk, reset):
if path.exists("dff_clkout"):
os.remove("dff_clkout")
os.system(cmd)
return Cosimulation("vvp -m ../myhdl.vpi dff_clkout", **locals())
return Cosimulation("vvp -m ../myhdl.vpi dff_clkout.o", **locals())

4
cosimulation/icarus/test/inc.py
View File

@ -2,11 +2,11 @@ import os
from myhdl import Cosimulation
cmd = "iverilog -o inc -Dn=%s " + \
cmd = "iverilog -o inc.o -Dn=%s " + \
"../../test/verilog/inc.v " + \
"../../test/verilog/dut_inc.v "
def inc(count, enable, clock, reset, n):
os.system(cmd % n)
return Cosimulation("vvp -m ../myhdl.vpi inc", **locals())
return Cosimulation("vvp -m ../myhdl.vpi inc.o", **locals())

4
cosimulation/icarus/test/test.py
View File

@ -4,14 +4,14 @@ from myhdl import Signal, Simulation, Cosimulation
from myhdl import delay, intbv, now
import os
cmd = "iverilog -o tb_test ./tb_test.v "
cmd = "iverilog -o tb_test.o ./tb_test.v "
os.system(cmd)
a = Signal(intbv(1))
b = Signal(intbv(2))
c = Signal(intbv(3))
cosim = Cosimulation("vvp -v -m ../myhdl.vpi tb_test", a=a, b=b, c=c)
cosim = Cosimulation("vvp -v -m ../myhdl.vpi tb_test.o", a=a, b=b, c=c)
def stimulus(a, b):
for i in range(10):