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Updated some README files

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This commit is contained in:
Jan Decaluwe 2013-05-20 13:49:03 +02:00
parent 70eff2ddb3
commit 6d46fedaa9
4 changed files with 5 additions and 10 deletions
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2
myhdl/test/conversion/general/README.txt
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@ -2,7 +2,7 @@ Conversion tests that should work with both VHDL and Verilog
------------------------------------------------------------
Requirements:
* cver, icarus, or GHDL
* cver, icarus, GHDL, or vcom/vlog (default)
* py.test
See the Makefile - it contains targets per simulator.

2
myhdl/test/conversion/toVHDL/README.txt
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@ -2,6 +2,6 @@ VHDL-specific conversion tests
------------------------------
Requirements:
* GHDL
* GHDL or vcom (default)
* py.test

9
myhdl/test/conversion/toVerilog/README.txt
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@ -5,12 +5,7 @@ Requirements:
* cver or icarus
* co-simulation with the target simulator enabled
cver is setup by default. You can change that by going into util.py
and using the Icarus definitions for the functions setupCosimulation
icarus is setup by default. You can change that by going into util.py
and using the cver definitions for the functions setupCosimulation
and verilogCompile.
The test suite should run without errors or failures with Cver
(GPLCVER_2.11a). However, with Icarus 0.8.1 some tests in test_dec and
test_signed fail. It has been found that Icarus 0.8 is currently
unreliable for signed arithmetic. It has been reported that the issues
are addressed in 0.9 development.

2
myhdl/test/conversion/toVerilog2/README.txt
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@ -2,7 +2,7 @@ Verilog-specific conversion tests
---------------------------------
Requirements:
* cver or icarus
* cver, icarus or vlog (default)
* py.test
See the Makefile - it contains targets per simulator.