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https://github.com/myhdl/myhdl.git
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shortcut logical
This commit is contained in:
jand
parent
0198118c21
commit
6d797db44f
@ -44,6 +44,12 @@ from myhdl._unparse import _unparse
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_converting = 0
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_profileFunc = None
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INPUT, OUTPUT, INOUT, \
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UNKNOWN, \
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NORMAL, DECLARATION, \
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ALWAYS, INITIAL, \
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BOOLEAN = range(9)
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class _error:
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pass
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_error.ArgType = "toVerilog first argument should be a classic function"
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@ -154,7 +160,9 @@ def _analyzeGens(top, genNames):
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symdict.update(f.f_locals)
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ast.symdict = symdict
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ast.name = genNames.get(id(g), genLabel.next() + "_BLOCK")
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v = _AnalyzeBlockVisitor(symdict, ast.sourcefile, ast.lineoffset)
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v = _NotSupportedVisitor(ast)
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compiler.walk(ast, v)
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v = _AnalyzeBlockVisitor(ast.symdict, ast.sourcefile, ast.lineoffset)
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compiler.walk(ast, v)
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ast.sigdict = v.sigdict
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ast.vardict = v.vardict
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@ -189,9 +197,20 @@ class _ToVerilogMixin(object):
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assert isinstance(node, ast.Node)
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if not test:
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self.raiseError(node, _error.Requirement, msg)
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def visitChildNodes(self, node, *args):
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for n in node.getChildNodes():
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self.visit(n, *args)
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class _NotSupportedVisitor(_ToVerilogMixin):
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def __init__(self, ast):
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self.sourcefile = ast.sourcefile
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self.lineoffset = ast.lineoffset
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self.symdict = ast.symdict
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self.toplevel = True
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def visitAssList(self, node, *args):
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self.raiseError(node, _error.NotSupported, "list assignment")
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def visitAssTuple(self, node, *args):
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@ -229,6 +248,46 @@ class _NotSupportedVisitor(_ToVerilogMixin):
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def visitTryFinally(self, node, *args):
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self.raiseError(node, _error.NotSupported, "try-finally statement")
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def visitAnd(self, node, context=UNKNOWN):
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if not context == BOOLEAN:
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self.raiseError(node, _error.NotSupported, "shortcutting logical and in non-boolean context")
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self.visitChildNodes(node, BOOLEAN)
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def visitOr(self, node, context=UNKNOWN):
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if not context == BOOLEAN:
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self.raiseError(node, _error.NotSupported, "shortcutting logical or in non-boolean context")
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self.visitChildNodes(node, BOOLEAN)
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def visitAssign(self, node, *args):
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if len(node.nodes) > 1:
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self.raiseError(node, _error.NotSupported, "multiple assignments")
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self.visit(node.nodes[0], *args)
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self.visit(node.expr, *args)
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def visitCallFunc(self, node, context=UNKNOWN):
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f = eval(_unparse(node.node), self.symdict)
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if f is bool:
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context = BOOLEAN
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self.visitChildNodes(node, context)
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def visitCompare(self, node, *args):
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if len(node.ops) != 1:
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self.raiseError(node, _error.NotSupported, "chained comparison")
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self.visitChildNodes(node, *args)
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def visitFunction(self, node, *args):
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if not self.toplevel:
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = False
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self.visitChildNodes(node, *args)
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def visitIf(self, node, *args):
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for test, suite in node.tests:
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self.visit(test, BOOLEAN)
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self.visit(suite, UNKNOWN)
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if node.else_:
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self.visit(node.else_, UNKNOWN)
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def getObj(node):
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if hasattr(node, 'obj'):
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@ -240,17 +299,11 @@ def getNrBits(obj):
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return obj._nrbits
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return None
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INPUT, OUTPUT, INOUT, UNKNOWN = range(4)
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NORMAL, DECLARATION = range(2)
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ALWAYS, INITIAL = range(2)
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class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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class _AnalyzeVisitor(_ToVerilogMixin):
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def __init__(self, symdict, sourcefile, lineoffset):
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self.sourcefile = sourcefile
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self.lineoffset = lineoffset
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self.toplevel = 1
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self.symdict = symdict
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self.vardict = {}
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self.inputs = Set()
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@ -284,8 +337,6 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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self.visit(node.expr, OUTPUT)
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def visitAssign(self, node, access=OUTPUT, *args):
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if len(node.nodes) > 1:
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self.raiseError(node, _error.NotSupported, "multiple assignments")
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target, expr = node.nodes[0], node.expr
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self.visit(target, OUTPUT)
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if isinstance(target, ast.AssName):
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@ -340,6 +391,8 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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ast.sourcefile = inspect.getsourcefile(func)
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ast.lineoffset = inspect.getsourcelines(func)[1]-1
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ast.symdict = func.func_globals.copy()
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v = _NotSupportedVisitor(ast)
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compiler.walk(ast, v)
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v = _AnalyzeFuncVisitor(ast.symdict, ast.sourcefile, ast.lineoffset, node.args)
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compiler.walk(ast, v)
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ast.sigdict = v.sigdict
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@ -366,8 +419,6 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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self.visit(arg, INPUT)
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def visitCompare(self, node, *args):
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if len(node.ops) != 1:
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self.raiseError(node, _error.NotSupported, "chained comparison")
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node.obj = bool()
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def visitConst(self, node, *args):
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@ -396,7 +447,7 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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self.labelStack.pop()
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def visitFunction(self, node, *args):
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raise AssertionError
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raise AssertionError("subclass must implement this")
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def visitGetattr(self, node, *args):
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self.visit(node.expr, *args)
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@ -428,8 +479,7 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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node.obj = __builtins__[n]
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def visitReturn(self, node, *args):
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self.visit(node.value)
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self.visit(node.value)
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def visitSlice(self, node, access=INPUT, kind=NORMAL, *args):
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self.visit(node.expr, access)
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@ -481,9 +531,6 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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sigdict[n] = v
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def visitFunction(self, node, *args):
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if not self.toplevel:
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = 0
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print node.code
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self.visit(node.code)
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self.kind = ALWAYS
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@ -508,6 +555,7 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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s._read = True
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def visitReturn(self, node, *args):
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### value should be None
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self.raiseError(node, _error.NotSupported, "return statement")
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@ -523,9 +571,6 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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self.returnObj = None
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def visitFunction(self, node, *args):
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if not self.toplevel:
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = 0
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argnames = node.argnames
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for i, arg in enumerate(self.args):
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if isinstance(arg, ast.Keyword):
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@ -1051,7 +1096,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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def visitReturn(self, node):
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self.write("disable %s;" % self.returnLabel)
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def visitSlice(self, node):
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if isinstance(node.expr, ast.CallFunc) and \
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node.expr.node.obj is intbv:
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@ -225,6 +225,43 @@ class TestNotSupported(unittest.TestCase):
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yield a, b, c
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z.next = a <= b < c
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self.check(g, z, a, b, c)
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def testShortcutAnd(self):
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a, b = [Signal(bool()) for i in range(2)]
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z = Signal(bool())
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def g(z, a, b):
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while 1:
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yield a
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if a:
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pass
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else:
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z.next = a and b
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self.check(g, z, a, b)
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def testShortcutOr(self):
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a, b, c = [Signal(bool()) for i in range(3)]
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z = Signal(bool())
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def g(z, a, b):
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while 1:
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yield a
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if a:
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pass
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else:
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z.next = a < (b or c)
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self.check(g, z, a, b)
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class TestMisc(unittest.TestCase):
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def test(self):
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a, b, c = [Signal(bool()) for i in range(3)]
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c = [1, 2]
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def g(a, b, c):
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yield a
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a.next = b is c
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x = g(a, b, c)
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x = toVerilog(g,a, b, c)
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