Solved bug 28

myhdl/conversion/_toVHDL.py

@@ -604,7 +604,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
                 else:
                     raise AssertionError("unexpected op %s" % op)
             elif isinstance(left.vhd, vhd_int) and isinstance(right.vhd, vhd_vector):
-                if isinstance(op, ast.Add, ast.Sub, ast.Mod, ast.FloorDiv):
+                if isinstance(op, (ast.Add, ast.Sub, ast.Mod, ast.FloorDiv)):
                     right.vhd.size = ns
                     node.vhdOri.size = ns
                 elif isinstance(op, ast.Mult):

myhdl/test/bugs/test_bug_28.py

@@ -0,0 +1,16 @@
+from myhdl import *
+
+def bug_28(dout, channel):
+    @always_comb
+    def comb():
+        dout.next = 0x8030 + (channel << 10)
+    return comb
+
+dout = Signal(intbv(0)[16:0])
+channel = Signal(intbv(0)[4:0])
+
+def test_bug_28():
+    try:
+        toVHDL(bug_28, dout, channel)
+    except:
+        raise