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conversion method

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This commit is contained in:
Jan Decaluwe 2016-03-12 08:57:38 +01:00
parent d06a94db0c
commit 6ecce37842
3 changed files with 12 additions and 2 deletions
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2
myhdl/__init__.py
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@ -84,6 +84,8 @@ class InstanceError(Error):
pass
class ModuleError(Error):
pass
class ModuleInstanceError(Error):
pass
class CosimulationError(Error):
pass
class ExtractHierarchyError(Error):

8
myhdl/_module.py
View File

@ -191,3 +191,11 @@ class _ModuleInstance(object):
def verify(self):
return myhdl.conversion.verify(self)
def convert(self, hdl='Verilog'):
if hdl == 'VHDL':
return myhdl.conversion._toVHDL.toVHDL(self)
elif hdl == 'Verilog':
return myhdl.conversion._toVerilog.toVerilog(self)
else:
raise ModuleInstanceError('unknown hdl %s' % hdl)

4
myhdl/conversion/_verify.py
View File

@ -139,9 +139,9 @@ class _VerificationClass(object):
if isinstance(func, _ModuleInstance):
if hdl == "VHDL":
inst = toVHDL(func)
inst = func.convert(hdl='VHDL')
else:
inst = toVerilog(func)
inst = func.convert(hdl='Verilog')
else:
if isinstance(func, _Module):
raise TypeError("Module %s: conversion should be on an instance" % func.__name__)