diff --git a/myhdl/__init__.py b/myhdl/__init__.py
index b55134ea..32620d49 100644
--- a/myhdl/__init__.py
+++ b/myhdl/__init__.py
@@ -84,6 +84,8 @@ class InstanceError(Error):
     pass
 class ModuleError(Error):
     pass
+class ModuleInstanceError(Error):
+    pass
 class CosimulationError(Error):
     pass
 class ExtractHierarchyError(Error):
diff --git a/myhdl/_module.py b/myhdl/_module.py
index 9bc6b38b..b0a98086 100644
--- a/myhdl/_module.py
+++ b/myhdl/_module.py
@@ -191,3 +191,11 @@ class _ModuleInstance(object):
 
     def verify(self):
         return myhdl.conversion.verify(self)
+
+    def convert(self, hdl='Verilog'):
+        if hdl == 'VHDL':
+            return myhdl.conversion._toVHDL.toVHDL(self)
+        elif hdl == 'Verilog':
+            return myhdl.conversion._toVerilog.toVerilog(self)
+        else:
+            raise ModuleInstanceError('unknown hdl %s' % hdl)
diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py
index 7867d7f0..7370f9ae 100644
--- a/myhdl/conversion/_verify.py
+++ b/myhdl/conversion/_verify.py
@@ -139,9 +139,9 @@ class  _VerificationClass(object):
 
         if isinstance(func, _ModuleInstance):
             if hdl == "VHDL":
-                inst = toVHDL(func)
+                inst = func.convert(hdl='VHDL')
             else:
-                inst = toVerilog(func)
+                inst = func.convert(hdl='Verilog')
         else:
             if isinstance(func, _Module):
                 raise TypeError("Module %s: conversion should be on an instance" % func.__name__)